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INTEGRATED CIRCUITS
DATA SHEET
SAA7110; SAA7110A One Chip Front-end 1 (OCF1)
Product specification File under Integrated Circuits, IC22 1995 Oct 18
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
CONTENTS 1 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 10 11 12 13 14 15 15.1 15.2 16 16.1 16.2 16.3 16.4 17 18 19 19.1 20 21 21.1 22 23 FEATURES APPLICATIONS GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION SYSTEM VIEW BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Analog input processing (see Fig.5) Analog control circuits Chrominance processing (see Fig.6) Luminance processing (see Fig.7) YUV-bus (digital outputs) Synchronization (see Fig.7) Clock generation circuit Power-on reset RTCO output GAIN CHARTS LIMITING VALUES CHARACTERISTICS TIMING OUTPUT FORMATS CLOCK SYSTEM Clock generation circuit Power-on control I2C-BUS DESCRIPTION I2C-bus format I2C-bus receiver/transmitter tables I2C-bus detail I2C-bus detail (continued) SOURCE SELECTION MANAGEMENT ANTI-ALIAS FILTER GRAPHS CORING FUNCTION Coring function adjustment by subaddress 06H to affect band filter output adjustment LUMINANCE FILTER GRAPHS I2C-BUS START SET-UP Remarks to Table 66 APPLICATION INFORMATION START-UP, SOURCE SELECT AND STANDARD DETECTION FLOW EXAMPLE 23.1 23.2 23.3 23.4 23.5 23.6 23.7 23.8 23.9 23.10 24 25 25.1 25.2 25.3 25.4 26 27 28
SAA7110; SAA7110A
CODE 0 STARTUP and STANDARD Procedure MODE 0 Source Select Procedure MODE 1 Source Select Procedure MODE 2 Source Select Procedure MODE 3 Source Select Procedure MODE 4 Source Select Procedure MODE 5 Source Select Procedure MODE 6 Source Select Procedure MODE 7 Source Select Procedure MODE 8 Source Select Procedure PACKAGE OUTLINE SOLDERING Introduction Reflow soldering Wave soldering Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
1995 Oct 18
2
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
1 FEATURES
SAA7110; SAA7110A
* Requires only one crystal (26.8 MHz) for all standards * Real time status information output (RTCO) * Brightness Contrast Saturation (BCS) control for the YUV-bus * Negation of picture possible * One user programmable general purpose switch on an output pin * Switchable between on-chip Clock Generation Circuit (CGC) and external CGC (SAA7197) * Power-on control * I2C-bus controlled. 2 APPLICATIONS
* Six analog inputs (6 x CVBS or 3 x Y/C or combinations) * Three analog processing channels * Three built-in analog anti-aliasing filters * Analog signal adding of two channels * Two 8-bit video CMOS analog-to-digital converters * Fully programmable static gain for the main channels or automatic gain control for the selected CVBS/Y channel * Selectable white peak control signal * Luminance and chrominance signal processing for PAL B/G, NTSC M and SECAM * Full range HUE control * Automatic detection of 50/60 Hz field frequency, and automatic switching between standards PAL and NTSC, SECAM forceable * Horizontal and vertical sync detection for all standards * Cross-colour reduction by chrominance comb filtering for NTSC or special cross-colour cancellation for SECAM * UV signal delay lines for PAL to correct chrominance phase errors * The YUV-bus supports a data rate of: - 780 x fh = 12.2727 MHz for 60 Hz (NTSC) - 944 x fh = 14.75 MHz for 50 Hz (PAL/SECAM) * Square pixel format with 768/640 active samples per line on the YUV-bus * CCIR 601 level compatible * 4 : 2 : 2 and 4 : 1 : 1 YUV output formats in 8-bit resolution * User programmable luminance peaking for aperture correction * Compatible with memory-based features (line-locked clock, square pixel) 4 QUICK REFERENCE DATA SYMBOL VDDA VDDD Tamb PARAMETER analog supply voltage digital supply voltage operating ambient temperature
* Desktop video * Multimedia * Digital television * Image processing * Video phone * Video picture grabbing. 3 GENERAL DESCRIPTION
The one chip front-end SAA7110; SAA7110A is a digital multistandard colour decoder (OCF1) on the basis of the DIG-TV2 system with two integrated Analog-to-Digital Converters (ADCs), a Clock Generation Circuit (CGC) and Brightness Contrast Saturation (BCS) control. The CMOS circuit SAA7110; SAA7110A, analog front-end and digital video decoder, is a highly integrated circuit for desktop video applications. The decoder is based on the principle of line-locked clock decoding. It operates square-pixel frequencies to achieve correct aspect ratio. Monitor controls are provided to ensure best display. The circuit is I2C-bus controlled.
MIN. 4.75 4.5 0 5.5 70
MAX. 5.25 V V C
UNIT
1995 Oct 18
3
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
5 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME SAA7110 SAA7110A 6 SYSTEM VIEW PLCC68 PLCC68 DESCRIPTION plastic leaded chip carrier; 68 leads plastic leaded chip carrier; 68 leads
SAA7110; SAA7110A
VERSION SOT188-2 SOT188-2
PC ISA - BUS
handbook, full pagewidth
I2C six video inputs ONE CHIP FRONT-END OCF1 clock VIDEO MEMORY CONTROLLER VMC VIDEO FRAME MEMORY
YUV - BUS
MGC821
Fig.1 System diagram.
1995 Oct 18
4
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Y Y VSSA2 to VSSA4 VDDA2 to VDDA4 VSS(S) AP 18, 14, 10 20, 16, 12 22 2 TEST CONTROL BLOCK SYNCHRONIZATION CIRCUIT Y 65 CLOCK GENERATION CIRCUIT 66 30 31 POWER-ON CONTROL 29 32 XTALO XTALI LLC2 CREF LLC RESET CLOCKS SP 1
7
Philips Semiconductors
One Chip Front-end 1 (OCF1)
BLOCK DIAGRAM
AOUT AI42 AI41 AI32 AI31 AI22 AI21 i.c.
23 11 13
BYPASS
4 15 17 19 21 7, 8, 9 CON I2C-BUS CONTROL 8 64 ANALOG PROCESSING C/CVBS CHROMINANCE CIRCUIT I2C-BUS INTERFACE 5 6
SA SDA SCL
GPSW (VBLK) UV7 to UV0 Y7 to Y0
AD2 AD3 BRIGHTNESS CONTRAST SATURATION CONTROL AND OUTPUT FORMATTER 55 to 62 45 to 50, 53, 54 63 42
ANALOG CONTROL Y/CVBS
LUMINANCE CIRCUIT UV
FEIN (MUXC) HREF
SAA7110 SAA7110A
SAA7110; SAA7110A
68, 52, 44, 34, 27 VDD
67, 51, 43, 35, 28 VSS
41 VS
38 HS
37 HSY
36
handbook, full pagewidth
40
39 PLIN (HL)
3
24 VDDA0
25
33
26
MGC820
Product specification
HCL
CGCE LFCO
ODD (VL)
RTCO
VSSA0
Fig.2 Block diagram.
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
8 PINNING SYMBOL SP AP RTCO SA SDA SCL i.c. i.c. i.c. VSSA4 AI42 VDDA4 AI41 VSSA3 AI32 VDDA3 AI31 VSSA2 AI22 VDDA2 AI21 VSS(S) AOUT VDDA0 VSSA0 LFCO PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 DESCRIPTION
SAA7110; SAA7110A
test pin input; (shift pin) connect to ground for normal operation test pin input; (action pin) connect to ground for normal operation Real Time Control Output. This pin is used to fit serially the increments of the HPLL and FSC-PLL and information of the PAL or SECAM sequence. I2C-bus slave address select input. LOW: slave address = 9CH for write, 9DH for read; HIGH = 9DH for write, 9FH for read. I2C-bus serial data input/output I2C-bus serial clock input reserved pin; do not connect reserved pin; do not connect reserved pin; do not connect ground for analog input 4 analog input 42 supply voltage (+5 V) for analog input 4 analog input 41 ground for analog input 3 analog input 32 supply voltage (+5 V) for analog input 3 analog input 31 ground for analog input 2 analog input 22 supply voltage (+5 V) for analog input 2 analog input 21 substrate ground analog test output; do not connect supply voltage (+5 V) for internal CGC (Clock Generation Circuit) ground for internal CGC Line Frequency Control output; this is the analog clock control signal driving the external CGC. The frequency is a multiple of the actual line frequency (nominally 7.375/6.13636 MHz). The signal has a triangular form with 4-bit accuracy. supply voltage (+5 V) ground Line-Locked Clock input/output (CGCE = 1, output; CGCE = 0, input). This is the system clock, its frequency is 1888 x fh for 50 Hz/625 lines per field systems and 1560 x fh for 60 Hz/525 lines per field systems; or variable input clock up to 32 MHz in input mode. Line-Locked Clock 12 output; fLLC2 = 0.5 x fLLC (CGCE = 1, output; CGCE = 0, high impedance). Clock reference input/output (CGCE = 1, output; CGCE = 0, input). This is a clock qualifier signal distributed by the internal or an external clock generator circuit (CGC). Using CREF all interfaces on the YUV-bus are able to generate a bus timing with identical phase.
VDD VSS LLC
27 28 29
LLC2 CREF
30 31
1995 Oct 18
6
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
SAA7110; SAA7110A
SYMBOL RESET
PIN 32
DESCRIPTION Reset active LOW input/output (CGCE = 1, output; CGCE = 0, input); sets the device into a defined state. All data outputs are in high impedance state. The I2C-bus is reset (waiting for START condition). Using the external CGC, the LOW period must be maintained for at least 30 LLC clock cycles. CGC Enable active HIGH input (CGCE = 1, on-chip CGC active; CGCE = 0, external CGC mode, use SAA7197). supply voltage (+5 V) ground Horizontal Clamping input/output pulse (programmable via I2C-bus bit PULIO: PULIO = 1, output; PULIO = 0, input). This signal is used to indicate the black level clamping period for the analog input interface. The beginning and end of its HIGH period (only in the output mode) can be programmed via the I2C-bus registers 03H, 04H in 50 Hz mode and registers 16H, 17H in 60 Hz mode, active HIGH. Horizontal Synchronization input/output indicator (programmable via I2C-bus bit PULIO: PULIO = 1, output; PULIO = 0, input). This signal is fed to the analog interface. The beginning and end of its HIGH period (only in the output mode) can be programmed via the I2C-bus registers 01H, 02H in 50 Hz mode and registers 14H, 15H in 60 Hz mode, active HIGH. Horizontal Synchronization output (programmable; the HIGH period is 128 LLC clock cycles). The position of the positive slope is programmable in 8 LLC increments over a complete line (64 s) via the I2C-bus register 05H in 50 Hz mode or register 18H in 60 Hz mode. PAL Identifier Not output; marks for demodulated PAL signals the inverted line (PLIN = LOW) and a non-inverted line (PLIN = HIGH) and for demodulated SECAM the DR line (PLIN = LOW) and the DB line (PLIN = HIGH). Select PLIN function via I2C-bus bit RTSE = 0. (H-PLL locked output; a HIGH state indicates that the internal PLL has locked. Select HL function via I2C-bus bit RTSE = 1). ODD/EVEN field identification output; a HIGH state indicates the odd field. Select ODD function via I2C-bus bit RTSE = 0. (Vertical Locked output; a HIGH state indicates that the internal Vertical Noise Limiter (VNL) is in a locked state. Select VL function via I2C-bus bit RTSE = 1). Vertical Synchronization input/output (programmable via I2C-bus bit OEHV: OEHV = 1, output; OEHV = 0, input). This signal indicates the vertical synchronization with respect to the YUV output. The high period of this signal is approximately six lines if the VNL function is active. The positive slope contains the phase information for a deflection controller, for example the TDA9150. In input mode this signal is used to synchronize the vertical gain and clamp blanking stage, active HIGH. Horizontal Reference output; this signal is used to indicate data on the digital YUV-bus. The positive slope marks the beginning of a new active line. The HIGH period of HREF is either 768 Y samples or 640 Y samples long depending on the detected field frequency (50/60 Hz mode). HREF is used to synchronize data multiplexer/demultiplexers. HREF is also present during the vertical blanking interval. ground supply voltage (+5 V)
CGCE VDD VSS HCL
33 34 35 36
HSY
37
HS
38
PLIN (HL)
39
ODD (VL)
40
VS
41
HREF
42
VSS VDD
43 44
1995 Oct 18
7
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
SAA7110; SAA7110A
SYMBOL Y7 Y6 Y5 Y4 Y3 Y2 VSS VDD Y1 Y0 UV7 UV6 UV5 UV4 UV3 UV2 UV1 UV0 FEIN (MUXC)
PIN 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 ground supply voltage (+5 V)
DESCRIPTION
Upper 6 bits of the 8-bit luminance (Y) digital output. As part of the digital YUV-bus (data rate LLC/2), or A/D2(3) output (data rate LLC/2) selectable via I2C-bus bit SQPB = 1.
Lower 2 bits of the 8-bit luminance (Y) digital output. As part of the digital YUV-bus (data rate LLC/2), or A/D2(3) output (data rate LLC/2) selectable via I2C-bus bit SQPB = 1.
8-bit digital UV (colour difference) output; multiplexed colour difference signal for U and V component of demodulated CVBS or chrominance signal. The format and multiplexing scheme can be selected via I2C-bus control. These signals are part of the digital YUV-bus (data rate LLC/2), or A/D3(2) output (data rate LLC/2) selectable via I2C-bus bit SQPB = 1.
Fast Enable input (active LOW); this signal is used to control fast switching on the digital YUV-bus. A high at this input forces the IC to set its Y and UV outputs to the high impedance state. To use this function set I2C-bus bits MS24 and MS34 and MUYC to LOW. (Multiplex Components input; control signal for the analog multiplexers for fast switching between locked Y/C signals or locked CVBS signals. FEIN automatically fixed to LOW (digital YUV-bus enabled), if one of the three MUXC functions are selected (MS24 or MS34 or MUYC = HIGH). General Purpose Switch output; the state of this signal is programmable via I2C-bus register 0Dh, bit 1. Select GPSW function via I2C-bus bit VBLKA = 0. (Vertical Blank test output; select VBLK via I2C-bus bit VBLKA = 1). Crystal oscillator output (to 26.8 MHz crystal); not used if TTL clock is used. Crystal oscillator input (from 26.8 MHz crystal) or connection of external oscillator with TTL compatible square wave clock signal. ground supply voltage (+5 V)
GPSW (VBLK) XTALO XTALI VSS VDD
64
65 66 67 68
1995 Oct 18
8
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
SAA7110; SAA7110A
64 GPSW (VBLK)
63 FEIN (MUXC)
65 XTALO
RTCO
66 XTALI
68 V DD
SDA
67 V SS
SCL
62 UV0
handbook, full pagewidth
VSSA4 10 AI42 11 VDDA4 12 AI41 13 VSSA3 14 AI32 15 VDDA3 16 AI31 17 VSSA2 18 AI22 19 VDDA2 20 AI21 21 VSS(S) 22 AOUT 23 VDDA0 24 VSSA0 25 LFCO 26
61 UV1
SA
AP 2
9
8
7
6
5
4
3
1
SP
i.c.
i.c.
i.c.
60 UV2 59 UV3 58 UV4 57 UV5 56 UV6 55 UV7 54 Y0 53 Y1
SAA7110 SAA7110A
52 V DD 51 V SS 50 Y2 49 Y3 48 Y4 47 Y5 46 Y6 45 Y7 44 V DD
VDD 27
VSS 28
LLC 29
LLC2 30
CREF 31
RESET 32
CGCE 33
VDD 34
VSS 35
HCL 36
HSY 37
HS 38
PLIN (HL) 39
ODD (VL) 40
VS 41
HREF 42
VSS 43
MGC822
Fig.3 Pin configuration.
1995 Oct 18
9
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
9 9.1 FUNCTIONAL DESCRIPTION Analog input processing (see Fig.5)
SAA7110; SAA7110A
The SAA7110; SAA7110A offers six analog signal inputs, two analog main channels with clamping circuit, analog amplifier, anti-alias filter and video CMOS ADC. A third analog channel also with clamping circuit, analog amplifier and anti-alias filter can be added or switched to both main channels directly before the ADCs. 9.2 Analog control circuits
handbook, halfpage
analog input level maximum range 8.8 dB minimum
controlled ADC input level
+2.8 dB 0 dB -6 dB
0 dB
The clamping control circuit controls the correct clamping of the analog input signals. The coupling capacitor is also used to store and filter the clamping voltage. The normal digital clamping level for luminance or CVBS signals is 64 and for chrominance signals is128. The gain control circuits generate via I2C-bus the static gain levels for the three analog amplifiers or controls one of these amplifiers automatically via a built-in Automatic Gain Control (AGC). The AGC is used to amplify a CVBS or Y signal to the required signal amplitude, matched to the ADCs input voltage range. The anti-alias filters are adapted to the clock frequency. The vertical blanking control circuit generates an I2C-bus programmable vertical blanking pulse. During the vertical blanking time gain and clamping control are frozen. The fast switch control circuit is used for special applications. 9.2.1 CLAMPING
MGC823
Fig.4 Automatic gain control range.
9.3
Chrominance processing (see Fig.6)
The 8-bit chrominance signal passes the input interface, the chrominance bandpass filter to eliminate DC components, and is finally fed to the multiplication inputs of a quadrature demodulator, where two subcarrier signals from the local oscillator DTO1 with 90 degrees phase shift are applied. The frequency is dependent on the present colour standard. The multiplier operates as a quadrature demodulator for all PAL and NTSC signals; it operates as a frequency down mixer for SECAM signals. The two multiplier output signals are converted to a serial UV data stream and applied to two low-pass filter stages, then to a gain controlled amplifier. A final multiplexed low-pass filter achieves, together with the preceding stages, the required bandwidth performance. The PAL and NTSC originated signals are applied to a comb filter. The signal originated from SECAM is fed through a Cloche filter (0 Hz centre frequency), a phase demodulator and a differentiator to obtain frequency demodulated colour difference signals. The SECAM signal is fed after de-emphasis to a cross-over switch, to provide both the serial transmitted colour difference signals. These signals are fed to the BCS control and finally to the output fomatter stage and to the output interface.
The coupling capacitor is used as clamp capacitance for each input. An internal digital clamp comparator generates the information concerning clamp-up or clamp-down. The clamping levels for the two ADC channels are adjustable over the 8-bit range (1 to 254). Clamping time in normal use is set with the HCL pulse at the back porch of the video signal. The clamping pulse HCL is user adjustable. 9.2.2 GAIN CONTROL (see Fig.4)
The luminance AGC can be used for every channel were luminance or CVBS is being received. AGC active time is the sync tip of the video signal. The sync tip pulse HSY is user adjustable. The AGC can be switched off and the gain for the three main input channels can be adjusted independently. Signal (white) peak control limits the gain at signal overshoots. The flow charts (see Figs 8 and 9) show more details of the AGC. The influence of supply voltage variation within the specified range is automatically eliminated by clamp and automatic gain control.
1995 Oct 18
10
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
9.4 Luminance processing (see Fig.7)
SAA7110; SAA7110A
The synchronization pulses are sliced and fed to the phase detectors where they are compared with the sub-divided clock frequency. The resulting output signal is applied to the loop filter to accumulate all phase deviations. Adjustable output signals HCL and HSY are generated in accordance with analog front end requirements. The output signals HS, VS, and PLIN are locked to the timing reference, guaranteed between the input signal and the HREF signal, as further improvements to the circuit may change the total processing delay. It is therefore not recommended to use them for applications which require absolute timing accuracy to the input signals. The loop filter signal drives an oscillator to generate the line frequency control signal LFCO. 9.7 Clock generation circuit
The 8-bit luminance signal, a digital CVBS format or a luminance format (S-VHS, HI8), is fed through a switchable prefilter. High frequency components are emphasized to compensate for loss. The following chrominance trap filter (fc = 4.43 or 3.58 MHz centre frequency selectable) eliminates most of the colour carrier signal, therefore, it must be bypassed for S-Video (S-VHS, HI8) signals. The high frequency components of the luminance signal can be peaked (control for sharpness improvement via I2C-bus) in two bandpass filters with selectable transfer characteristics. A coring circuit with selectable characteristics improves the signal once more. This signal is then added to the original (unpeaked) signal. A switchable amplifier achieves common DC amplification, because the DC gains are different in both chrominance trap modes. The improved luminance signal is fed via the variable delay to the BCS control and the output interface. 9.5 YUV-bus (digital outputs)
The 16-bit YUV-bus transfers digital data from the output interfaces to a feature box, or a field memory, a digital colour space converter (SAA 7192 DCSC) or a video enhancement and digital-to-analog processor (SAA7165 VEDA2). The outputs are controlled by an output enable chain (FEIN on pin 63). The YUV data rate equals LLC2. Timing is achieved by marking each second positive rising edge of the clock LLC in conjunction with CREF (clock reference). The output signals Y7 to Y0 are the bits of the digital luminance signal. The output signals UV7 to UV0 are the bits of multiplexed colour difference signals (B-Y) and (R-Y). The frame in the format tables is the time, required to transfer a full set of samples. In the event of 4 : 2 : 2 format two luminance samples are transmitted in comparison to one U and one V sample within the frame. The time frames are controlled by the HREF signal. Fast enable is achieved by setting input FEIN to LOW. The signal is used to control fast switching on the digital YUV-bus. HIGH on this pin forces the Y and UV outputs to a high-impedance state. 9.6 Synchronization (see Fig.7)
The internal CGC generates all clock signals required for the one chip front-end. The output signal LFCO is a digital-to-analog converted signal provided by the horizontal PLL. It is the multiple of the line frequency (7.38 MHz = 472 x fh in 50 Hz systems and 6.14 MHz = 360 x fh in 60 Hz systems). Internally the LFCO signal is multiplied by a factor of 2 or 4 in the PLL circuit (including phase detector, loop filtering, VCO and frequency divider) to obtain the LLC and LLC2 output clock signals. The rectangular output clocks have a 50% duty factor. It is also possible to operate the OCF1 with an external CGC (SAA7197) providing the signals LLC and CREF. The selection of the internal/external CGC will be controlled by the CGCE input signal. 9.8 Power-on reset
Power-on reset is activated at power-on (using only internal CGC), when the supply voltage decreases below 3.5 V. The indicator output RESET is LOW for a time. The RESET signal can be applied to reset other circuits of the digital TV system. 9.9 RTCO output
The real time control and status output signal contains serial information about actual system clock, subcarrier frequency and PAL/SECAM sequence. The signal can be used for various applications in external circuits, for example, in a digital encoder to achieve clean encoding.
The pre-filtered luminance signal is fed to the synchronization stage. It's bandwidth is reduced to 1 MHz in a low-pass filter. 1995 Oct 18 11
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ANALOG CONTROL
CLAMP CONTROL WIPA GLIM i.c. i.c. i.c. 9 8 7 CLTS CLS2 CLS3 CLL2n CLS4 CLL3n VSS(S) 22 CROSS MULTIPLEXER YSEL CSEL TWO2 TWO3
Philips Semiconductors
One Chip Front-end 1 (OCF1)
VDDA2 to VDDA4 VSSA2 to VSSA4 AI42 AI41
20, 16, 12 18, 14, 10 11 13 SOURCE SWITCH CLAMP CIRCUIT ANALOG AMPLIFIER ANTI-ALIAS FILTER BYPASS SWITCH TEST SELECTOR 23 AOUT
AINS4 AIND4 AI32 AI31 15 17 SOURCE SWITCH
REFS4
FUSE
AOSL
CLAMP CIRCUIT
ANALOG AMPLIFIER
ANTI-ALIAS FILTER
BYPASS SWITCH
FAST SWITCH ADDER
ADC
AINS3 AIND3 AI22 AI21 19 21 SOURCE SWITCH
REFS3
FUSE
CLAMP CIRCUIT
ANALOG AMPLIFIER
ANTI-ALIAS FILTER
BYPASS SWITCH
FAST SWITCH ADDER
ADC
AINS2 AIND2
REFS2
WISL GAS2 IVAL GAS3 WVAL GAD2 GUDL GAD3 WIRS WRSE
FUSE
GAIN CONTROL
ANTI-ALIAS CONTROL GACO GAI2 GAI3 GAI4 IWIP IGAI
VERTICAL BLANKING CONTROL
FAST SWITCH CONTROL
HOLD WIPE SBOT GASL
VBPS VBPR VBCO
MUYC MX24 MS24 MX34 MS34 MUD1 MUD2
SAA7110; SAA7110A
handbook, full pagewidth
MGC824
Product specification
Fig.5 Analog input processing and analog control part.
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63 55 to 62 INPUT INTERFACE CHROMINANCE BANDPASS QUADRATURE DEMODULATOR LOW-PASS GAIN CONTROL LOW-PASS OUTPUT FORMATTER AND INTERFACE 45 to 50, 53, 54 HUEC DISCRETE TIME OSCILLATOR (DTO1) AND DIVIDER CHCV CKTQ CKTS LFIS LOOPFILTER PI2 CLOCH FILTER OFTS SQPB CHSB HRMV OEYC HRFS OEHV COMB FILTERS AND SECAM RECOMBINATION BRIGHTNESS CONTRAST SATURATION CONTROL BRIG CONT SATN 42 HREF FEIN (MUXC) UV7 to UV0 Y7 to Y0 BYPS CHRS LOOP FILTER PI1 BURST GATE ACCUMULATOR PHASE DEMODULATOR AMPLITUDE DETECTOR VDD 68, 52, 44, 34, 27 SEQA SEQA SESE PLSE SEQUENCE PROCESSOR DIFFERENTIATOR
Philips Semiconductors
One Chip Front-end 1 (OCF1)
handbook, full pagewidth
13
VSS
67, 51, 43, 35, 28
ALTD
COLO SECS
STANDARD CONTROL
DE-EMPHASIS
CHROMINANCE CIRCUIT
CODE SXCR
MGC825
SAA7110; SAA7110A
Product specification
Fig.6 Multi-standard decoder part.
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LUMINANCE CIRCUIT
CHROMINANCE TRAP VARIABLE BANDPASS FILTER WEIGHTING AND ADDING STAGE VARIABLE DELAY PREFILTER CORING PREF AP SP 2 1 TEST CONTROL BLOCK BYPS BFBY PREF BPSS CORI APER YDEL MATCHING AMPLIFIER POWER-ON CONTROL 32 RESET CLOCK(3 to 0) 31 PREFILTER SYNC SYNC SLICER PHASE DETECTOR FINE PHASE DETECTOR COARSE LOOP FILTER 2 DELAY ADJUSTMENT LINE-LOCKED CLOCK GENERATOR 29 30 CREF LLC LLC2
Philips Semiconductors
One Chip Front-end 1 (OCF1)
Fig.7 Luminance and synchronization part.
handbook, full pagewidth
14
I CONTROL VBLKA SSTB GPSW HS6B HS6S HC6B HC6S PULIO OEHV SCEN IDEL HSYB HSYS HCLB HCLS HPHI HP6I
2C-BUS
SYNCHRONIZATION CIRCUIT
HLCK VTRC
HPLL HLCK DISCRETE TIME OSCILLATOR (DTO2) CRYSTAL CLOCK GENERATOR 66 65 XTALI XTALO
HLCK STTC
FIDT
GPSW (VBLK)
64
I2C-BUS INTERFACE
COUNTER
VERTICAL PROCESSOR
VNOI FSEI AUFD
CLOCK GENERATION CIRCUIT
DAC6
DAC4
26
LFCO
SAA7110; SAA7110A
4 SA
5
6
36 37 38 39 3 HCL HS RTCO HSY PLIN (HL)
41 VS
40 ODD (VL)
25 VSSA0
24
33
MGC826
SCL SDA
CGCE
VDDA0
Product specification
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
10 GAIN CHARTS
handbook, full pagewidth
SAA7110; SAA7110A
ANALOG IN
ADC
NO BLANKING ACTIVE
1
VBLK
0
<- CLAMP
GAIN ->
1
HCL
0
1
HSY
0
CLAA = 1
CLAA = 0 1 >SBOT 0 1 > WIPE 0
1
0
CLAU = 1
CLAU = 0
+ CLAMP
- CLAMP
NO CLAMP
+ GAIN
- GAIN
- GAIN
SLOW + GAIN
MGC827
CLAU = clamp up. VBLK = vertical blanking pulse. WIPE = white peak level (adjustable). SBOT = sync bottom level (adjustable). CLL = clamp level (adjustable). CLAA = clamp active. HSY = horizontal sync pulse. HCL = horizontal clamp pulse.
Fig.8 Clamp and gain flow chart.
1995 Oct 18
15
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
SAA7110; SAA7110A
handbook, full pagewidth
analog input MSB amplifier anti-alias amplifier ADC8 decoder input no action 1 VBLK 1 0 0 2 LSB 6
X
1 1 1 0
HSY
0
0 0 0 1
>WIPE
1
>WIPE
0
WRSE
X=0 WIRS 0
X=1
1
+4/F *IWIP STOP
+4/L
-IVAL *IGAI
+IVAL
-WVAL *IWIP +/- 0
gain accumulator (20 bits) actual gain value 8-bit (AGV) [-3/+6 dB] 1 0
X = system variable (start with logic 0). Y = IAGV-FGVI > GUDL. VBLK = vertical blanking pulse. HSY = horizontal sync pulse. SBOT = sync bottom level (adjustable). WIPE = white peak level (adjustable). IVAL = integration value gain (adjustable). WVAL = integration value WIPE (adjustable). IGAI = integration factor gain (adjustable). IWIP = integration factor WIPE (adjustable). AGV = actual gain value. FGV = frozen gain value. GUDL = gain update level (adjustable). WRSE = white peak reset enable. WIRS = white peak reset select. L = line. F = field.
X 1
HSY 1
0 0
Y
AGV
update gain value 8-bit
FGV
MGC828
Fig.9 Luminance AGC flow chart.
1995 Oct 18
16
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
SAA7110; SAA7110A
11 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); all ground pins and all supply pins connected together. SYMBOL VDDA VDDD VI(A) VI(D) Vdiff Tstg Tamb Tamb(bias) Ptot Vesd Note 1. Compare with typical total power consumption in Chapter "Characteristics". 2. Equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. 12 CHARACTERISTICS VDDD = 5 V; VDDA = 5 V; Tamb = 25 C; unless otherwise specified. SYMBOL Supplies VDDA VDDD IDDA(tot) IDDD(tot) Ptot Iclamp Vi(p-p) Zi Ci ct B diff Gdiff fLLC DLE ILE 1995 Oct 18 analog supply voltage digital supply voltage total analog supply current total digital supply current total power dissipation 4.75 4.5 - - - -2 0.5 200 - fi < 5 MHz at -3 dB - - 5.0 5.0 - - 1.2 - 1.0 - - -50 5.25 5.5 150 250 1.7 V V mA mA W A V k pF dB PARAMETER CONDITIONS MIN. TYP. MAX. UNIT PARAMETER analog supply voltage digital supply voltage analog input voltage digital input voltage voltage difference between VSSAall and VSSall storage temperature operating ambient temperature operating ambient temperature under bias total power dissipation electrostatic discharge all pins note 2 CONDITIONS MIN. -0.5 -0.5 -0.5 -0.5 - -65 0 -10 VDDA = VDDD = 7 V; note 1 - -2000 MAX. +7.0 +7.0 +7.0 +7.0 100 +150 70 +80 2.5 +2000 UNIT V V V V mV C C C W V
Analog part clamping current input voltage (peak-to-peak value), AC coupling required input impedance input capacitance channel crosstalk VI = 1.25 V DC Ccouple = 10 nF clamping current off +2 1.38 - 10 - - - - 16
2
Analog-to-digital converters analog bandwidth differential phase differential gain ADC clock rate DC differential linearity error DC integral linearity error 17 15 2 2 -
1
MHz deg % MHz LSB LSB
amplifier + AAF = bypass - amplifier + AAF = bypass - 11 - -
- -
1
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
SAA7110; SAA7110A
SYMBOL Digital inputs VIL VIH VIL(clk) VIH(clk) VIH(XTALI) VIL(n) VIH(n) ILI Ci(clk) Ci(I/O) Ci(n) VLFCO VOL VOH VOL(clk) VOH(clk)
PARAMETER
CONDITIONS
MIN. -0.5 3.0 -0.5 2.4 3.0 -0.5 2.0 - - - - - - - - - - - - - - - - - -
TYP.
MAX.
UNIT
LOW level input voltage SDA and SCL HIGH level input voltage SDA and SCL LOW level input voltage for clocks HIGH level input voltage for clocks HIGH level input voltage XTALI LOW level input voltage all other inputs HIGH level input voltage all other inputs input leakage current input capacitance for clocks input capacitance input capacitance all other inputs I/Os at high impedance
+1.5 VDD + 0.5 +0.6 VDD + 0.5 VDD + 0.5 +0.8 VDD + 0.5 10 10 8 8
V V V V V V V A pF pF pF
- -
Digital outputs LFCO output voltage (peak-to-peak value) LOW level output voltage HIGH level output voltage LOW level output voltage for clocks HIGH level output voltage for clocks note 1 note 2 note 2 1.4 0 2.4 -0.5 2.6 2.6 0.6 VDD +0.6 VDD + 0.5 V V V V V
Clock input timing (LLC) Tcy tr tf tSU;DAT tHD;DAT tHD;FEIN tHD;OTHER cycle time duty factor for tLLCH/Tcy rise time fall time Vi = 0.6 to 2.4 V Vi = 2.4 to 0.6 V 31 40 - - - - - - - - - - 45 60 5 5 - - - - ns % ns ns
Control and CREF input timing (note 3) input data set-up time input data hold time input data hold time for FEIN input data hold time all other inputs note 3 11 3 3 6 ns ns ns ns
1995 Oct 18
18
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
SAA7110; SAA7110A
SYMBOL
PARAMETER
CONDITIONS
MIN. - - - -
TYP.
MAX.
UNIT
Data and control output timing (note 4) CL(data) CL(control) tHD;DAT tPD(data) output load capacitance (data, HREF and VS) output load capacitance (control) output data hold time propagation delay from negative edge of LLC (data, HREF and VS) propagation delay from negative edge of LLC (control) propagation delay from negative edge of LLC (to 3-state) CL = 15 pF CL = 50 pF 15 7.5 13 - 50 25 - 29 pF pF ns ns
tPD(control) tPD(Z))
CL = 25 pF note 5
- -
- -
29 15
ns ns
Clock output timing (LLC and LLC2) CL(LLC) Tcy tr tf td output load capacitance cycle time duty factors for tLLCH/tLLC and tLLC2H/tLLC2 rise time fall time delay time LLC output to LLC2 output 0.6 to 2.6 V 2.6 to 0.6 V LLC LLC2 15 31.5 63 40 - - - - - - - - - 40 45 90 60 5 5 8 pF ns ns % ns ns ns
- Vi = 1.5 V; CLLC/LLC2 = 40 pF; note 6 CL = 15 pF CL = 40 pF 4 -
Data qualifier output timing (CREF) tHD;CREF tPD;CREF output hold time propagation delay from positive edge of LLC - - - 20 ns ns
Horizontal PLL fHnom fH/fHnom nominal line frequency permissible static deviation 50 Hz field 60 Hz field 50 Hz field 60 Hz field Subcarrier PLL fHnom fH/fHnom nominal subcarrier frequency lock-in range PAL NTSC - - 400 4433618 - 3579545 - - - Hz Hz Hz - - - - 15625 15734 - - - - 5.6 6.7 Hz Hz % %
1995 Oct 18
19
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
SAA7110; SAA7110A
SYMBOL Crystal oscillator fn f/fn T/fn
PARAMETER
CONDITIONS -
MIN.
TYP. -
MAX.
UNIT
nominal frequency permissible frequency deviation permissible frequency deviation with temperature
3rd harmonic
26.8
MHz
-50 x 10-6 - -20 x 10-6 -
+50 x 10-6 +20 x 10-6
CRYSTAL SPECIFICATION (X1); note 7 Tamb CL Rs C1 C0 Notes 1. The LFCO output level must be measured with a load circuit of 10 k in parallel with 15 pF. 2. The levels must be measured with load circuits, the loads depend on the type of output stage. Control outputs (except HREF and VS); 1.2 k at 3 V (TTL load); CL = 25 pF: data outputs (plus HREF and VS); 1.2 k at 3 V (TTL load); CL = 50 pF. 3. Other control input signals are CGCE, VS, SA, HCL and HSY. 4. Data output signals are YUV (15 to 0). Control output signals are HREF, VS, HS, HSY, HCL, RTCO, PLIN (HL), ODD (VL) and GPSW0 (VBLK). The effects of rise and fall times are included in the calculation of tHD;DAT, tPD and tPDZ. Timings and levels refer to drawings and conditions illustrated in Fig.10. 5. The minimum propagation delay from 3-state to data active related to falling edge of LLC is 0 ns. 6. LLC2 is not active while CGCE = 0. 7. Philips catalogue number 9922 520 30004. Table 1 Processing delay TYPICAL ANALOG DELAY AI21 TO ADCIN (AOUT) (ns) 10 30 30 + 40 30 + 50 248 DIGITAL DELAY ADCIN (AOUT) TO YUVOUT (1/LLC) (YDEL = 0; CAD2/3 = 1) operating ambient temperature load capacitance series resonance resistance motional capacitance parallel capacitance 0 8 - - - - - 50 70 - 80 C pF fF pF
1.1 20% - 3.5 20% -
FUNCTION
Without amplifier or anti-alias filter With amplifier, without anti-alias filter With amplifier plus anti-alias filter (50 Hz) With amplifier plus anti-alias filter (60 Hz)
1995 Oct 18
20
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
13 TIMING
SAA7110; SAA7110A
handbook, full pagewidth
Tcy 2.4 V 1.5 V 0.6 V tLLCH tf tr
CLOCK INPUT LLC
INPUTS CONTROL
INPUT CREF
OUTPUTS YUV, HREF, VS AND HS
OUTPUTS YUV (to 3-state)
,,, ,,,,,,,,, ,,,,,,,,,,,,, ,,,,,,,,, ,,,,,,,,,,,,, ,,, ,,,,, ,,,,, ,,, ,,,
tSU;DAT tHD;DAT tSU;DAT tHD;DAT tHD;DAT tOHD tPD tOHD tPDZ Tcy tLLCL tf tLLCH tPD tr
2.0 V 0.8 V
2.0 V 0.8 V
2.4 V 0.6 V
CLOCK OUTPUT LLC
2.6 V 1.5 V 0.6 V
OUTPUT CREF
,,, ,,,, ,, ,,, ,,,, ,,
tOHD tOHD tdLLC2
MGC829
2.4 V 0.6 V
CLOCK OUTPUT LLC2
2.6 V 1.5 V 0.6 V
Fig.10 Clock/data timing.
1995 Oct 18
21
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
SAA7110; SAA7110A
0
handbook, full pagewidth
62 x 2/LLC CVBS burst
HSY HSY +191 programming range (step size: 2/LLC) HCL HCL programming range (step size: 2/LLC) +127 -128 -64
processing delay CVBS->YUV (1)
Y output HREF (50 Hz) 768 x 2/LLC 30 x 2/LLC PLIN (50 Hz) 4/LLC HS (50 Hz) 64 x 2/LLC 0 18 x 2/LLC 176 x 2/LLC 94 x 2/LLC
HS (50 Hz) +117 programming range (step size: 8/LLC) HREF (60 Hz) 640 x 2/LLC HS (60 Hz)
-118
18 x 2/LLC 140 x 2/LLC
64 x 2/LLC HS (60 Hz) +97 programming range (step size: 8/LLC) 0 -97
MGC830
(1) See Table 1. HRMV = 1 and HRFS = 0.
Fig.11 Horizontal timing.
1995 Oct 18
22
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
SAA7110; SAA7110A
handbook, full pagewidth
LL27 CREF INTERNAL BUS CLOCK
START OF ACTIVE LINE HREF
Yn
0
1
2
3
4
UVn
U0
V0
U1
V1
U2
ONE BUS CYCLE END OF ACTIVE LINE HREF Yn (50 Hz) UVn V762 U764 V764 U766 V766 763 764 765 766 767
Yn (60 Hz) UVn
635
636
637
638
639
V634
U636
V636
U638
V638
MGC831
Fig.12 HREF timing.
1995 Oct 18
23
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
SAA7110; SAA7110A
handbook, full pagewidth
a: 1st field(1) input CVBS HREF
625
1
2
3
4
5
6
7
8
9
533 x 2/LLC VS ODD 2 x 2/LLC
b: 2nd field(1) input CVBS HREF
313
314
315
316
317
318
319
320
321
61 x 2/LLC VS ODD 2 x 2/LLC
a: 1st field(2) input CVBS HREF
525
1
2
3
4
5
6
7
8
9
441 x 2/LLC VS ODD 2 x 2/LLC
b: 2nd field(2) input CVBS HREF
263
264
265
266
267
268
269
270
271
51 x 2/LLC VS ODD
MGC832
2 x 2/LLC
(1) Nominal input signal 50 Hz. (2) Nominal input signal 60 Hz. HRMV = 1 and HRFS = 0.
Fig.13 Vertical timing.
1995 Oct 18
24
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
SAA7110; SAA7110A
handbook, full pagewidth LLC
to 3-state CREF
from 3-state
HREF tSU;DAT FEIN tOHD YUV
MGC833
tHD;DAT
tPD
Fig.14 FEIN timing.
Table 2
Digital output control FEIN 0 0 1 YUV (15 : 0) Z active Z
OEYC 0 1 X
handbook, full pagewidth
transmitted once per line SEQUENCE RESERVED LOW HIGH HPLL-INCR. RESERVED 31
63 67
FSCPLL-INCR.
RESERVED (50 Hz SYSTEMS) 276 (60 Hz SYSTEMS) 188
MGC834
128 BIT NO.: TIME SLOT:
13 01
14
0
4
45
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
14 19
RTCO sequence is generated in LLC/4. For transmission LLC/2 timing is required.
Fig.15 Real time control output timing.
1995 Oct 18
25
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
14 OUTPUT FORMATS Table 3 Output formats PIXEL BYTE SEQUENCE 4 : 1 : 1 FORMAT Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 U7 U6 V7 V6 0 0 0 0 0 Y7 Y7 Y5 Y4 Y3 Y2 Y1 Y0 U5 U4 V5 V4 0 0 0 0 1 0 data rate Y U V LLC2 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 U3 U2 V3 V2 0 0 0 0 2 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 U1 U0 V1 V0 0 0 0 0 3 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 U7 U6 V7 V6 0 0 0 0 4 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 U5 U4 V5 V4 0 0 0 0 5 4 sample frequency LLC2 LLC4 LLC4 LLC2 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 U3 U2 V3 V2 0 0 0 0 6 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 U1 U0 V1 V0 0 0 0 0 7
SAA7110; SAA7110A
BUS SIGNAL Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 UV7 UV6 UV5 UV4 UV3 UV2 UV1 UV0 Y frame UV frame
PIXEL BYTE SEQUENCE 4 : 2 : 2 FORMAT Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 U7 U6 U5 U4 U3 U2 U1 U0 0 0 data rate Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 V7 V6 V5 V4 V3 V2 V1 V0 1 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 U7 U6 U5 U4 U3 U2 U1 U0 2 2 LLC2 LLC8 LLC8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 V7 V6 V5 V4 V3 V2 V1 V0 3 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 U7 U6 U5 U4 U3 U2 U1 U0 4 4 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 V7 V6 V5 V4 V3 V2 V1 V0 5
sample frequency
1995 Oct 18
26
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
SAA7110; SAA7110A
handbook, full pagewidth
+255 +235
+255 +240 +212
blue 100% blue 75%
+255 +240 +212
red 100% red 75%
+128
LUMINANCE 100%
+128 U-COMPONENT
+128 V-COMPONENT
+44 +16 0 +16 0
yellow 75% yellow 100%
+44 +16 0
cyan 75% cyan 100%
MGC835
a. Y output range.
b. U output range (B-Y).
c. Y output range (R-Y).
CCIR 601 digital levels.
Fig.16 YUV output signal range.
handbook, full pagewidth
quartz (3rd harmonic) 26.8 MHz XTALO 65 C= SAA7110 10 pF XTALI
XTALO
65
SAA7110A
XTALI
SAA7110 SAA7110A
66
66
L = 10 H +/-20% C= 10 pF C= 1 nF
MGC836
a. with quartz crystal.
b. with external clock.
Fig.17 Oscillator application.
1995 Oct 18
27
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
15 CLOCK SYSTEM 15.1 Clock generation circuit CLOCK Table 4
SAA7110; SAA7110A
System clock frequencies FREQUENCY (MHz) 50 Hz XTAL LLC LLC2 LLC4 LLC8 26.8 29.5 14.75 7.375 3.6875 60 Hz 26.8 24.545454 12.272727 6.136136 3.068181
The internal CGC generates the system clocks LLC, LLC2 and the clock reference signal CREF. The internally generated LFCO (triangular waveform) is multiplied by four via the analog PLL (including phase detector, loop filter, VCO and frequency divider). The rectangular output signals have a 50% duty factor.
handbook, full pagewidth
LFCO
BAND PASS FC = LLC/4
ZERO CROSS DETECTION
PHASE DETECTION
LOOP FILTER
OSCILLATOR
LLC
DIVIDER 1/2
DIVIDER 1/2
LLC2
DELAY
MGC837
CREF
Fig.18 Clock generation circuit.
1995 Oct 18
28
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
15.2 Power-on control
SAA7110; SAA7110A
Power-on reset is activated at power-on (using only internal CGC) and if the supply voltage falls below 3.5 V. The RESET signal can be applied to reset other circuits of the digital TV system.
handbook, full pagewidth
POC VDD ANALOG
POC VDD DIGITAL
LLC POC LOGIC CGCE DELAY CONTROL RESET
CLOCK I/O CONTROL
CLOCK OUTPUT ACTIVE CONTROL
MGC838
Fig.19 Power-on control circuit.
Table 5
Power-on control sequence PIN OUTPUT STATUS Y7 to Y0, UV7 to UV0, RTCO, PLIN, ODD, GPSW, SDA, HREF, HS, VS, HCL and HSY in high impedance state LLC, LLC2 and CREF in HIGH state FUNCTION direct switching to high impedance (outputs) or input mode (I/Os) for 20 to 200 ms
INTERNAL POWER-ON CONTROL SEQUENCE Directly after power-on asynchronous reset
Start synchronous I2C-bus reset sequence
LLC, LLC2 and CREF active
starting I2C-bus reset sequence SA0DH = 7DH (VTRC = 0, RTSE = 1, HRMV = 1, SSTB = 0, SECS = 1) SA0EH = 00H (HPLL = 0, OEHV = 0, OEYC = 0, CHRS = 0, GPSW = 0) SA31H = 00H (AOSL 1 : 0 = 00, WIRS = 0, WRSE = 0, SQPB = 0, VBLKA = 0, PULIO = 0)
Status after I2C-bus reset Y7 to Y0, UV7 to UV0, HREF and HS held in high impedance state VS, HCL and HSY held in input function mode
Status after power-on control sequence 1995 Oct 18
RTCO, PLIN, ODD, GPSW and SDA active
after power-on (reset sequence) a complete I2C-bus transmission is required
29
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
16 I2C-BUS DESCRIPTION 16.1 S Table 6 I2C-bus format SLAVE ADDRESS ACK SUBADDRESS ACK
SAA7110; SAA7110A
DATA (n bytes)
ACK
P
Description of I2C-bus format CODE DESCRIPTION START condition 1001 110Xb (SA = LOW) or 1001 111Xb (SA = HIGH) acknowledge generated by the slave subaddress byte, see Table 7 data byte, see Table 7; note 1 STOP condition read/write control bit: X = 0, order to write (the circuit is slave receiver) X = 1, order to read (the circuit is slave transmitter)
S Slave address ACK Subaddress Data P X
Slave address Subaddress
9CH for write, 9DH for read (SA = 0) 9EH for write, 9FH for read (SA = 1 00H to 19H decoder part 1AH to 1FH reserved 20H to 34H front-end part
Note 1. If more than one byte DATA is transmitted then the auto-increment of the subaddress is performed.
1995 Oct 18
30
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
16.2 I2C-bus receiver/transmitter tables
SAA7110; SAA7110A
Table 7 OCF1 RECEIVER Slave address 10011100b, 9CH (SA = 0) and 10011110b, 9EH (SA = 1) REGISTER FUNCTION SUB ADD(1) DATA BYTE(2) D7 D6 D5 D4 D3 D2 D1 D0
DMSD-SQP + BSC slave receiver (SU 00H to 19H) Increment delay HSY begin 50 Hz HSY stop 50 Hz HCL begin 50 Hz HCL stop 50 Hz HSY after PHI1 50 Hz Luminance control Hue control Colour killer threshold QUAM (PAL/NTSC) Colour killer threshold SECAM PAL switch sensitivity SECAM switch sensitivity Gain control chrominance Standard/mode control I/O and clock control Control #1 Control #2 Chrominance gain reference Chrominance saturation 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 007 IDEL7 015 HSYB7 023 HSYS7 031 HCLB7 039 HCLS7 047 HPHI7 055 BYPS 006 IDEL6 014 HSYB6 022 HSYS6 030 HCLB6 038 HCLS6 046 HPHI6 054 PREF 005 IDEL5 013 HSYB5 021 HSYS5 029 HCLB5 037 HCLS5 045 HPHI5 053 BPSS1 004 IDEL4 012 HSYB4 020 HSYS4 028 HCLB4 036 HCLS4 044 HPHI4 052 BPSS0 003 IDEL3 011 HSYB3 019 HSYS3 027 HCLB3 035 HCLS3 043 HPHI3 051 CORI1 002 IDEL2 010 HSYB2 018 HSYS2 026 HCLB2 034 HCLS2 042 HPHI2 050 CORI0 001 IDEL1 009 HSYB1 017 HSYS1 025 HCLB1 033 HCLS1 041 HPHI1 049 APER1 000 IDEL0 008 HSYB0 016 HSYS0 024 HCLB0 032 HCLS0 040 HPHI0 048 APER0
063 062 061 060 059 058 057 056 HUEC7 HUEC6 HUEC5 HUEC4 HUEC3 HUEC2 HUEC1 HUEC0 071 CKTQ4 079 CKTS4 087 PLSE7 095 SESE7 103 COLO 111 VTRC 119 HPLL 127 AUFD 135 XXX 070 CKTQ3 078 CKTS3 086 PLSE6 094 SESE6 102 LFIS1 110 XXX 118 XXX 126 FSEL 134 XXX 069 CKTQ2 077 CKTS2 085 PLSE5 093 SESE5 101 LFIS0 109 XXX 117 XXX 125 SXCR 133 XXX 068 CKTQ1 076 CKTS1 084 PLSE4 092 SESE4 100 XXX 108 XXX 116 OEHV 124 SCEN 132 XXX 067 CKTQ0 075 CKTS0 083 PLSE3 091 SESE3 099 XXX 107 RTSE 115 OEYC 123 XXX 131 XXX 066 XXX 074 XXX 082 PLSE2 090 SESE2 098 XXX 106 HRMV 114 CHRS 122 YDEL2 130 HRFS 065 XXX 073 XXX 081 PLSE1 089 SESE1 097 XXX 105 SSTB 113 XXX 121 YDEL1 129 VNOI1 064 XXX 072 XXX 080 PLSE0 088 SESE0 096 XXX 104 SECS 112 GPSW 120 YDEL0 128 VNOI0
143 142 141 140 139 138 137 136 CHCV7 CHCV6 CHCV5 CHCV4 CHCV3 CHCV2 CHCV1 CHCV0 151 SATN7 150 SATN6 149 SATN5 148 SATN4 147 SATN3 146 SATN2 145 SATN1 144 SATN0
1995 Oct 18
31
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
SAA7110; SAA7110A
REGISTER FUNCTION Luminance contrast HSY begin 60 Hz HSY stop 60 Hz HCL begin 60 Hz HCL stop 60 Hz HSY after PHI1 60 Hz Luminance brightness
SUB ADD(1) 13 14 15 16 17 18 19
DATA BYTE(2) D7 D6 D5 D4 D3 D2 D1 D0
159 158 157 156 155 154 153 152 CONT7 CONT6 CONT5 CONT4 CONT3 CONT2 CONT1 CONT0 167 HS6B7 175 HS6S7 183 HC6B7 191 HC6S7 199 HP6I7 207 BRIG7 166 HS6B6 174 HS6S6 182 HC6B6 190 HC6S6 198 HP6I6 206 BRIG6 165 HS6B5 173 HS6S5 181 HC6B5 189 HC6S5 197 HP6I5 205 BRIG5 164 HS6B4 172 HS6S4 180 HCLB4 188 HC6S4 196 HP6I4 204 BRIG4 163 HS6B3 171 HS6B3 179 HC6B3 187 HC6S3 195 HP6I3 203 BRIG3 162 HS6B2 170 HS6S2 178 HC6B2 186 HC6S2 194 HP6I2 202 BRIG2 161 HS6B1 169 HS6S1 177 HC6B1 185 HC6S1 193 HP6I1 201 BRIG1 160 HS6B0 168 HS6S0 176 HC6B0 184 HC6S0 192 HP6I0 200 BRIG0
DUAD slave receiver (SU 20H to 32H) Analog control #1 Analog control #2 Mixer control #1 Clamping level control 21 Clamping level control 22 Clamping level control 31 Clamping level control 32 Gain control analog #1 White peak control Sync bottom control Gain control analog #2 Gain control analog #3 Mixer control #2 Integration value gain 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 007 AIND4 015 VBCO 006 AIND3 014 MS34 005 AIND2 013 MX241 021 CSEL 004 FUSE1 012 MX240 020 YSEL 003 FUSE0 011 MS24 019 MUYC 002 AINS4 010 REFS4 018 CLTS 001 AINS3 009 REFS3 017 MX341 000 AINS2 008 REFS2 016 MX340
023 022 GACO1 GACO0
031 030 029 028 027 026 025 024 CLL217 CLL216 CLL215 CLL214 CLL213 CLL212 CLL211 CLL210 039 038 037 036 035 034 033 032 CLL227 CLL226 CLL225 CLL224 CLL223 CLL222 CLL221 CLL220 047 046 045 044 043 042 041 040 CLL317 CLL316 CLL315 CLL314 CLL313 CLL312 CLL311 CLL310 055 054 053 052 051 050 049 048 CLL327 CLL326 CLL325 CLL324 CLL323 CLL322 CLL321 CLL320 063 HOLD 071 WIPE7 079 SBOT7 087 IWIP1 095 IGAI1 103 CLS4 111 IVAL7 062 GASL 070 WIPE6 078 SBOT6 086 IWIP0 094 IGAI0 102 XXX 110 IVAL6 061 GAI25 069 WIPE5 077 SBOT5 085 GAI35 093 GAI45 101 CLS3 109 IVAL5 060 GAI24 068 WIPE4 076 SBOT4 084 GAI34 092 GAI44 100 CLS2 108 IVAL4 059 GAI23 067 WIPE3 075 SBOT3 083 GAI33 091 GAI43 099 XXX 107 IVAL3 058 GAI22 066 WIPE2 074 SBOT2 082 GAI32 090 GAI42 098 XXX 106 IVAL2 057 GAI21 065 WIPE1 073 SBOT1 081 GAI31 089 GAI41 097 TWO3 105 IVAL1 056 GAI20 064 WIPE0 072 SBOT0 080 GAI30 088 GAI40 096 TWO2 104 IVAL0
1995 Oct 18
32
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
SAA7110; SAA7110A
REGISTER FUNCTION Vertical blanking pulse set Vertical blanking pulse reset ADCs gain control Mixer control #3 Integration value white peak Mixer control #4 Gain update level Notes
SUB ADD(1) 2E 2F 30 31 32 33 34
DATA BYTE(2) D7 119 VBPS7 127 VBPR7 135 XXX 143 AOSL1 151 WVAL7 159 OFTS 167 MUD2 D6 118 VBPS6 126 VBPR6 134 WISL 142 AOSL0 150 WVAL6 158 XXX 166 MUD1 D5 117 VBPS5 125 VBPR5 133 GAS3 141 WIRS 149 WVAL5 157 CHSB 165 GUDL5 D4 116 VBPS4 124 VBPR4 132 GAD31 140 WRSE 148 WVAL4 156 XXX 164 GUDL4 D3 115 VBPS3 123 VBPR3 131 GAD30 139 SQPB 147 WVAL3 155 CAD3 163 GUDL3 D2 114 VBPS2 122 VBPR2 130 GAS2 138(3) AFCCS 146 WVAL2 154 CAD2 162 GUDL2 D1 113 VBPS1 121 VBPR1 129 GAD21 137 VBLKA 145 WVAL1 153 XXX 161 GUDL1 D0 112 VBPS0 120 VBPR0 128 GAD20 136 PULIO 144 WVAL0 152 XXX 160 GUDL0
1. Subaddresses to be reset: 0D to 7DH, 0E and 31 to 00H after RESET = 0 (CGCE = 0) or power-on (CGCE = 1). 2. All reserved XXX-bits must be set to LOW, XX-bit is don't care. 3. AFCCS bit does not exist in SAA7110A due to advanced anti-alias filter characteristic, don't care (XX). Table 8 OCF1 TRANSMITTER: Byte number 0 (transmitted if SSTB = 0 or after RESET has been 0) Slave address 10011101b, 9DH (SA = 0) and 10011111b, 9FH (SA = 1 VERSION STATUS BYTE ID7 to ID0; note 1 Note 1. ID7 to ID0 indicates the version number of the IC, for example SAA7110A V1 = 01H. Table 9 OCF1 TRANSMITTER: Byte number 1 (transmitted if SSTB = 1) Slave address 10011101b, 9DH (SA = 0) and 10011111b, 9FH (SA = 1) STATUS BYTE FUNCTION See Table 10 for explanation of bits D7 STTC D6 HLCK D5 FIDT D4 GLIM D3 XXX D2 WIPA D1 ALTD D0 CODE D7 ID7 D6 ID6 D5 ID5 D4 ID4 D3 ID3 D2 ID2 D1 ID1 D0 ID0
1995 Oct 18
33
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
Table 10 Explanation of bits shown in Table 9 BIT STTC HLCK FIDT GLIM XXX WIPA ALTD CODE 16.3 DESCRIPTION
SAA7110; SAA7110A
Status bit for horizontal time constant: LOW = TV time constant; HIGH = VCR time constant. Status bit for locked horizontal frequency: LOW = locked; HIGH = unlocked. Identification bit for detected field frequency: LOW = 50 Hz; HIGH = 60 Hz. Gain value for active luminance is limited (maximum or minimum), active HIGH. reserved White peak loop is activated, active HIGH. Status HIGH: line alternating colour burst has been detected (PAL or SECAM). Status HIGH: any colour signal has been detected.
I2C-bus detail
The I2C-bus receiver slave address is 9CH/9EH. DMSD-SQP slave receiver (SU 00H to 19H). 16.3.1 SUBADDRESS 00 (DATA BYTE 007 to 000)
Table 11 Increment delay IDEL DECIMAL MULTIPLIER -1 -195 -236 -256 Notes 1. A sign bit, designated A08 and internally set to HIGH, indicates values are always negative. 2. The horizontal PLL does not operate in this condition. The system clock frequency is set to a value fixed by the last update and is within 7.1% of the nominal frequency. DELAY TIME (STEP SIZE = 4/LLC) -4 -780 max. value for 60 Hz -944 max. value for 50 Hz -1024 outside central counter(2) CONTROL BITS(1) IDEL7 1 0 0 0 IDEL6 1 0 0 0 IDEL5 1 1 0 0 IDEL4 1 1 1 0 IDEL3 1 1 0 0 IDEL2 1 1 1 0 IDEL1 1 0 0 0 IDEL0 1 1 0 0
1995 Oct 18
34
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
16.3.2 SUBADDRESS 01 (DATA BYTE 015 to 008)
SAA7110; SAA7110A
Table 12 Horizontal synchronization begin 50 Hz (HSYB) DECIMAL MULTIPLIER +191 -64 16.3.3 DELAY TIME (STEP SIZE = 2/LLC) -382 +128 CONTROL BITS HSYB7 HSYB6 HSYB5 HSYB4 HSYB3 HSYB2 HSYB1 HSYB0 1 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0
SUBADDRESS 02 (DATA BYTE 023 to 016)
Table 13 Horizontal synchronization stop 50 Hz (HSYS) DECIMAL MULTIPLIER +191 -64 16.3.4 DELAY TIME (STEP SIZE = 2/LLC) -382 +128 CONTROL BITS HSYS7 HSYS6 HSYS5 HSYS4 HSYS3 HSYS2 HSYS1 HSYS0 1 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0
SUBADDRESS 03 (DATA BYTE 031 to 024)
Table 14 Horizontal clamping begin 50 Hz (HCLB) DECIMAL MULTIPLIER +127 -128 16.3.5 DELAY TIME (STEP SIZE = 2/LLC) -254 +256 CONTROL BITS HCLB7 HCLB6 HCLB5 HCLB4 HCLB3 HCLB2 HCLB1 HCLB0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0
SUBADDRESS 04 (DATA BYTE 039 to 032)
Table 15 Horizontal clamping stop 50 Hz (HCLS) DECIMAL MULTIPLIER +127 -128 DELAY TIME (STEP SIZE = 2/LLC) -254 +256 CONTROL BITS HCLS7 HCLS6 HCLS5 HCLS4 HCLS3 HCLS2 HCLS1 HCLS0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0
1995 Oct 18
35
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
16.3.6 SUBADDRESS 05 (DATA BYTE 047 to 040)
SAA7110; SAA7110A
Table 16 Horizontal synchronization start after PHI1 50 Hz (HPHI) DECIMAL MULTIPLIER +127 +118 +117 -118 -119 -128 DELAY TIME (STEP SIZE = 8/LLC) forbidden; outside available central counter range -32 s (max. negative value) +31.7 s (max. positive value) forbidden; outside available central counter range CONTROL BITS HPHI7 0 0 0 1 1 1 HPHI6 1 1 1 0 0 0 HPHI5 1 1 1 0 0 0 HPHI4 1 1 1 0 0 0 HPHI3 1 0 0 1 1 0 HPHI2 1 1 1 0 0 0 HPHI1 1 1 0 1 0 0 HPHI0 1 0 1 0 1 0
1995 Oct 18
36
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
16.3.7 SUBADDRESS 06 (DATA BYTE 055 to 048)
SAA7110; SAA7110A
Table 17 Luminance control FUNCTION Aperture factor (APER); data bits D1 and D0 0 1 2 3 0 0.25 0.5 1.0 APER1 = 0; APER0 = 0 APER1 = 0; APER0 = 1 APER1 = 1; APER0 = 0 APER1 = 1; APER0 = 1 CONTROL BITS
Corner correction (CORI) LSBs in 8-bit; data bits D3 and D2 0 1 2 3 0 (OFF) 1 2 3 CORI1 = 0; CORI0 = 0 CORI1 = 0; CORI0 = 1 CORI1 = 1; CORI0 = 0 CORI1 = 1; CORI0 = 1
Aperture bandpass; centre frequency (BPSS); data bits D4 and D5 4.6 MHz (50 Hz) 4.3 MHz (50 Hz) 3.0 MHz (50 Hz) 3.2 MHz (50 Hz) 3.8 MHz (60 Hz) 3.4 MHz (60 Hz) 2.5 MHz (60 Hz) 2.7 MHz (60 Hz) BPSS1 = 0; BPSS0 = 0 BPSS1 = 0; BPSS0 = 1 BPSS1 = 1; BPSS0 = 0 BPSS1 = 1; BPSS0 = 1
Prefilter active (PREF); data bit D6 Bypassed Active Chrominance trap bypass (BYPS); data bit D7 Active Bypassed 16.3.8 CVBS mode S-Video mode BYPS = 0 BYPS = 1 PREF = 0 PREF = 1
SUBADDRESS 07 (DATA BYTE 063 to 056)
Table 18 Hue phase control HUEC CONTROL BITS HUE PHASE (DEGREES) HUEC7 +178.6 0 -180 0 0 1 HUEC6 1 0 0 HUEC5 1 0 0 HUEC4 1 0 0 HUEC3 1 0 0 HUEC2 1 0 0 HUEC1 1 0 0 HUEC0 1 0 0
1995 Oct 18
37
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
16.3.9 SUBADDRESS 08 CONTROL NUMBER 1 (DATA BYTE 071 to 064)
SAA7110; SAA7110A
Table 19 Colour killer threshold QUAM (PAL/NTSC) THRESHOLD (reference is nominal burst amplitude = 0 dB) -30 dB -24 dB -18 dB CONTROL BITS CKTQ4 1 1 0 CKTQ3 1 0 0 CKTQ2 1 0 0 CKTQ1 1 0 0 CKTQ0 1 0 0
16.3.10 SUBADDRESS 09 CONTROL NUMBER 2 (DATA BYTE 079 to 072) Table 20 Colour killer threshold SECAM THRESHOLD (reference is nominal burst amplitude = 0 dB) -30 dB -24 dB -18 dB 16.3.11 SUBADDRESS 0A (DATA BYTE 087 to 080) Table 21 PAL switch sensitivity CONTROL BITS SENSITIVITY PLSE7 Low Medium High(1) Note 1. Sensitivity HIGH means immediate sequence correction. 16.3.12 SUBADDRESS 0B (DATA BYTE 095 to 088) Table 22 SECAM switch sensitivity CONTROL BITS SENSITIVITY SESE7 Low Medium High(1) Note 1. Sensitivity HIGH means immediate sequence correction. 1995 Oct 18 38 1 1 0 SESE6 1 0 0 SESE5 1 0 0 SESE4 1 0 0 SESE3 1 0 0 SESE2 1 0 0 SESE1 1 0 0 SESE0 1 0 0 1 1 0 PLSE6 1 0 0 PLSE5 1 0 0 PLSE4 1 0 0 PLSE3 1 0 0 PLSE2 1 0 0 PLSE1 1 0 0 PLSE0 1 0 0 CONTROL BITS CKTS4 1 1 0 CKTS3 1 0 0 CKTS2 1 0 0 CKTS1 1 0 0 CKTS0 1 0 0
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
16.3.13 SUBADDRESS 0C (DATA BYTE 103 to 096) Table 23 Gain control chrominance FUNCTION AGC loop filter (LFIS); data bits D6 and D5 Slow time constant Medium time constant Fast time constant Actual chrominance gain frozen Colour on (COLO); data bit D7 Automatic colour killer Colour forced on 16.3.14 SUBADDRESS 0D (DATA BYTE 111 to 104) Table 24 Standard/mode control FUNCTION SECAM mode bit (SECS); data bit D0 Other standards SECAM mode Status byte select (SSTB); data bit D1 Status byte = 0 (see transmitter) Status byte = 1 (see transmitter) HREF position select (HRMV); data bit D2 HREF position as SAA7191 (8 LLC2 later) HREF normal position Real time outputs mode select (RTSE); data bit D3 PLIN switched to output pin 39 ODD switched to output pin 40 HL switched to output pin 39 VL switched to output pin 40 TV/VCR mode select (VTRC); data bit D7 TV mode VTR mode
SAA7110; SAA7110A
CONTROL BITS
LFIS1 = 0; LFIS0 = 0 LFIS1 = 0; LFIS0 = 1 LFIS1 = 1; LFIS0 = 0 LFIS1 = 1; LFIS0 = 1
COLO = 0 COLO = 1
CONTROL BITS
SECS = 0 SECS = 1
SSTB 0 SSTB = 1
HRMV = 0 HRMV = 1
RTSE = 0 RTSE = 1
VTRC = 0 VTRC = 1
1995 Oct 18
39
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
16.3.15 SUBADDRESS 0E (DATA BYTE 119 to 112) Table 25 I/O and clock control FUNCTION General purpose switch (GPSW); data bit D0 Switches directly pin 64 GPSW (application dependent); VBLKA = 0 Select chrominance input (CHRS); data bit D2 Controlled by BYPS (subaddress 06) normal position Digital chrominance input switched to second input channel (see Fig.20) Output enable YUV-data (OEYC); data bit D3 YUV bus high impedance/input Output YUV-bus active Output enable horizontal/vertical synchronization (OEHV); data bit D4 HS, HREF and VS high impedance/inputs Output HS, HREF and VS active Horizontal PLL clock (HPLL); data bit D7 PLL closed PLL open, horizontal frequency fixed 16.3.16 SUBADDRESS 0F (DATA BYTE 127 to 120) Table 26 Control number 1 FUNCTION
SAA7110; SAA7110A
CONTROL BITS
GPSW = 0 GPSW = 1
CHRS = 0 CHRS = 1
OEYC = 0 OEYC = 1
OEHV = 0 OEHV = 1
HPLL = 0 HPLL = 1
CONTROL BITS
Luminance delay compensation; steps in 2/LLC (YDEL); data bits D2, D1 and D0 0 steps 3 steps -4 steps YDEL2 = 0; YDEL1 = 0; YDEL0 = 0 YDEL2 = 0; YDEL1 = 1; YDEL0 = 1 YDEL2 = 1; YDEL1 = 0 YDEL1 = 0
Enable or disable of sync and clamp pulses; HSY and HCL (SCEN); data bit D4 Disable sync and clamp (set to HIGH) Enable sync and clamp SECAM cross colour reduction (SXCR); data bit D5 Reduction off Reduction on Field selection (FSEL); data bit D6 50 Hz, 625 lines 60 Hz, 525 lines Automatic field detection(AUFD); data bit D7 Field state directly controlled via FSEL Automatic field detection 1995 Oct 18 40 AUFD = 0 AUFD = 1 FSEL = 0 FSEL = 1 SXCR = 0 SXCR = 1 SCEN = 0 SCEN = 1
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
16.3.17 SUBADDRESS 10 (DATA BYTE 135 to 128) Table 27 Control number 2 FUNCTION Vertical noise reduction (VNOI); data bits D1 and D0 Normal mode Search mode Free running mode Vertical noise reduction bypassed HREF select HRFS (HRFS); data bit D2 HREF matched to YUV output HREF matched to CVBS input 16.3.18 SUBADDRESS 11 (DATA BYTE 143 to 136) Table 28 Chrominance gain reference value CONTROL BITS REFERENCE VALUE CHCV7 Maximum CCIR-level for PAL CCIR-level for NTSC Minimum 1 0 0 0 CHCV6 1 1 0 0 CHCV5 1 0 1 0 CHCV4 1 1 0 0 CHCV3 1 1 1 0
SAA7110; SAA7110A
CONTROL BITS
VNOI1 = 0; VNOI0 = 0 VNOI1 = 0; VNOI0 = 1 VNOI1 = 1; VNOI0 = 0 VNOI1 = 1; VNOI0 = 1
HRFS = 0 HRFS = 1
CHCV2 1 0 1 0
CHCV1 1 0 0 0
CHCV0 1 1 0 0
16.3.19 SUBADDRESS 12 (DATA BYTE 150 to 144) Table 29 Chrominance saturation control CONTROL BITS GAIN SATN7 1.999 Maximum 1 CCIR-level 0 colour off -1 inverse chrominance -2 inverse chrominance 0 0 0 1 1 SATN6 1 1 0 1 0 SATN5 1 0 0 0 0 SATN4 1 0 0 0 0 SATN3 1 0 0 0 0 SATN2 1 0 0 0 0 SATN1 1 0 0 0 0 SATN0 1 0 0 0 0
1995 Oct 18
41
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
16.3.20 SUBADDRESS 13 (DATA BYTE 158 to 152) Table 30 Luminance contrast control
SAA7110; SAA7110A
CONTROL BITS GAIN CONT7 CONT6 CONT5 1.999 Maximum 70 CCIR-level 1 0 luminance off -1 inverse luminance -2 inverse luminance 0 0 0 0 1 1 1 1 1 0 1 0 1 0 0 0 0 0 CONT4 1 0 0 0 0 0 CONT3 1 0 0 0 0 0 CONT2 1 1 0 0 0 0 CONT1 1 1 0 0 0 0 CONT0 1 0 0 0 0 0
16.3.21 SUBADDRESS 14 (DATA BYTE 167 to 160) Table 31 Horizontal synchronization begin 60 Hz (HS6B) DECIMAL MULTIPLIER +191 -64 DELAY TIME (step size = 2/LLC) -382 +128 CONTROL BITS HS6B7 1 1 HS6B6 0 1 HS6B5 1 0 HS6B4 1 0 HS6B3 1 0 HS6B2 1 0 HS6B1 1 0 HS6B0 1 0
16.3.22 SUBADDRESS 15 (DATA BYTE 175 to 168) Table 32 Horizontal synchronization stop 60 Hz (HS6S) DECIMAL MULTIPLIER +191 -64 DELAY TIME (step size = 2/LLC) -382 +128 CONTROL BITS HS6S7 1 1 HS6S6 0 1 HS6S5 1 0 HS6S4 1 0 HS6S3 1 0 HS6S2 1 0 HS6S1 1 0 HS6S0 1 0
16.3.23 SUBADDRESS 16 (DATA BYTE 183 to 176) Table 33 Horizontal clamping begin 60 Hz (HC6B) DECIMAL MULTIPLIER +127 -128 DELAY TIME (step size = 2/LLC) -254 +256 CONTROL BITS HC6B7 0 1 HC6B6 1 0 HC6B5 1 0 HC6B4 1 0 HC6B3 1 0 HC6B2 1 0 HC6B1 1 0 HC6B0 1 0
1995 Oct 18
42
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
16.3.24 SUBADDRESS 17 (DATA BYTE 191 to 184) Table 34 Horizontal clamping stop 60 Hz (HC6S) DECIMAL MULTIPLIER +127 -128 DELAY TIME (step size = 2/LLC) -254 +256
SAA7110; SAA7110A
CONTROL BITS HC6S7 0 1 HC6S6 1 0 HC6S5 1 0 HC6S4 1 0 HC6S3 1 0 HC6S2 1 0 HC6S1 1 0 HC6S0 1 0
16.3.25 SUBADDRESS 18 (DATA BYTE 199 to 192) Table 35 Horizontal synchronization start after PHI1 60 Hz (HP6I) DECIMAL MULTIPLIER +127 +98 +97 -97 -98 -128 DELAY TIME (step size = 8/LLC) forbidden; outside available central counter range -32 s (max. negative value) +31.7 s (max. positive value) forbidden; outside available central counter range CONTROL BITS HP6I7 0 0 0 1 1 1 HP6I6 1 1 1 0 0 0 HP6I5 1 1 1 0 0 0 HP6I4 1 0 0 1 1 0 HP6I3 1 0 0 1 1 0 HP6I2 1 0 0 1 1 0 HP6I1 1 1 0 1 1 0 HP6I0 1 0 1 1 0 0
16.3.26 SUBADDRESS 19 (DATA BYTE 207 to 200) Table 36 Luminance brightness control CONTROL BITS OFFSET BRIG7 255 (bright) 139 (CCIR-level) 128 0 (dark) 1 1 1 0 BRIG6 1 0 0 0 BRIG5 1 0 0 0 BRIG4 1 0 0 0 BRIG3 1 1 0 0 BRIG2 1 0 0 0 BRIG1 1 1 0 0 BRIG0 1 1 0 0
1995 Oct 18
43
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
16.4 I2C-bus detail (continued)
SAA7110; SAA7110A
DUAD slave receiver (SU 20H to 32H). 16.4.1 SUBADDRESS 20 (DATA BYTE 007 to 000)
Table 37 Analog control #1 FUNCTION Analog input select 2 (AINS2); data bit D0 Analog input AI22 selected Analog input AI21 selected Analog input select 3 (AINS3); data bit D1 Analog input AI32 selected Analog input AI31 selected Analog input select 4 (AINS4); data bit D2 Analog input AI42 selected Analog input AI41 selected Analog function select (FUSE); data bits D4 and D3 Amplifier plus anti-alias filter bypassed Amplifier active Amplifier plus anti-alias filter active Analog input disable 2 (AIND2); data bit D5 Analog inputs 2 enabled Analog inputs 2 disabled Analog input disable 3 (AIND3); data bit D6 Analog inputs 3 enabled Analog inputs 3 disabled Analog input disable 4 (AIND4); data bit D7 Analog inputs 4 enabled Analog inputs 4 disabled AIND4 = 0 AIND4 = 1 AIND3 = 0 AIND3 = 1 AIND2 = 0 AIND2 = 1 FUSE1 = 0; FUSE0 = 0 FUSE1 = 0; FUSE0 = 1 FUSE1 = 1; FUSE0 = 0 FUSE1 = 1; FUSE0 = 1 AINS4 = 0 AIND4 = 1 AINS3 = 0 AINS3 = 1 AINS2 = 0 AINS2 = 1 CONTROL BITS
1995 Oct 18
44
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
16.4.2 SUBADDRESS 21 (DATA BYTE 015 to 008)
SAA7110; SAA7110A
Table 38 Analog control #2 FUNCTION Reference select channel 2 (REFS2); data bit D0 Automatic clamping active Reference level selected Reference select channel 3 (REFS3); data bit D1 Automatic clamping active Reference level selected Reference select channel 4 (REFS4); data bit D2 Automatic clamping active Reference level selected MUXC select channel 24 (MS24); data bit D3 Analog MUX2 controlled by MX24 Analog MUX2 controlled by MUXC Analog MUX2 control (MX24); data bits D5 and D4 Adder mode Channel 2 on; channel 4 off Channel 2 off; channel 4 on Both channels off MUXC select channel 34 (MS34); data bit D6 Analog MUX3 controlled by MX34 Analog MUX3 controlled by MUXC Vertical blanking control off (VBCO); data bit D7 Vertical blanking on Vertical blanking off VBCO = 0 VBCO = 1 MS34 = 0 MS34 = 1 MX241 = 0; MX240 = 0 MX241 = 0; MX240 = 1 MX241 = 1; MX240 = 0 MX241 = 1; MX240 = 1 MS24 = 0 MS24 = 1 REFS4 = 0 REFS4 = 1 REFS3 = 0 REFS3 = 1 REFS2 = 0 REFS2 = 1 CONTROL BITS
1995 Oct 18
45
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
16.4.3 SUBADDRESS 22 (DATA BYTE 023 to 016)
SAA7110; SAA7110A
Table 39 Mixer control #1 FUNCTION Analog MUX3 control (MX34); data bits D1 and D0 Adder mode Channel 3 on; channel 4 off Channel 3 off; channel 4 on Both channels off Clamping function test (CLTS); data bit D2 Normal clamping mode CLAAn and CLAUn adjusted via CLL32 value for testing (do not use) Fast digital multiplexing channel 2/3 active (MUYC); data bit D3 Normal mode on CHR channel Multiplex mode on CHR channel for test purposes only (do not use) Luminance select (YSEL); data bit D4 ADC 2 to CVBS ADC 3 to CVBS Chrominance select (CSEL); data bit D5 ADC 3 to CHR (MUXC not inverse; MUYC = 1) ADC 2 to CHR (MUXC inverse; MUYC = 1) Automatic gain control (GACO); data bits D7 and D6 Automatic gain control off Automatic gain control channel 2 Automatic gain control channel 3 Automatic gain control channel 4 16.4.4 SUBADDRESS 23 (DATA BYTE 031 to 024) GACO1 = 0; GACO0 = 0 GACO1 = 0; GACO0 = 1 GACO1 = 1; GACO0 = 0 GACO1 = 1; GACO0 = 1 CSEL = 0 CSEL = 1 YSEL = 0 YSEL = 1 MUYC = 0 MUYC = 1 CLTS = 0 CLTS = 1 MX341 = 0; MX340 = 0 MX341 = 0; MX340 = 1 MX341 = 1; MX340 = 0 MX341 = 1; MX340 = 1 CONTROL BITS
Table 40 Clamping level control 21 CLL21 CONTROL BITS DECIMAL CLAMP LEVEL CLL217 1 64 128 254 0 0 1 1 CLL216 0 1 0 1 CLL215 0 0 0 1 CLL214 0 0 0 1 CLL213 0 0 0 1 CLL212 0 0 0 1 CLL211 0 0 0 1 CLL210 1 0 0 0
1995 Oct 18
46
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
16.4.5 SUBADDRESS 24 (DATA BYTE 039 to 032)
SAA7110; SAA7110A
Table 41 Clamping level control 22 CLL22 CONTROL BITS DECIMAL CLAMP LEVEL CLL227 1 64 128 254 16.4.6 0 0 1 1 CLL226 0 1 0 1 CLL225 0 0 0 1 CLL224 0 0 0 1 CLL223 0 0 0 1 CLL222 0 0 0 1 CLL221 0 0 0 1 CLL220 1 0 0 0
SUBADDRESS 25 (DATA BYTE 047 to 040)
Table 42 Clamping level control 31 CLL31 CONTROL BITS DECIMAL CLAMP LEVEL CLL317 1 64 128 254 16.4.7 0 0 1 1 CLL316 0 1 0 1 CLL315 0 0 0 1 CLL314 0 0 0 1 CLL313 0 0 0 1 CLL312 0 0 0 1 CLL311 0 0 0 1 CLL310 1 0 0 0
SUBADDRESS 26 (DATA BYTE 055 to 048)
Table 43 Clamping level control 32 CLL32 CONTROL BITS DECIMAL CLAMP LEVEL CLL327 1 64 128 254 0 0 1 1 CLL326 0 1 0 1 CLL325 0 0 0 1 CLL324 0 0 0 1 CLL323 0 0 0 1 CLL322 0 0 0 1 CLL321 0 0 0 1 CLL320 1 0 0 0
1995 Oct 18
47
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
16.4.8 SUBADDRESS 27 (DATA BYTE 063 to 056); GAIN CONTROL ANALOG #1
SAA7110; SAA7110A
Table 44 Static gain control channel 2 (GAI2); data bits D5 to D0 DECIMAL GAIN MULTIPLIER (step size = 0.19 dB) 0 15 31 47 63 -2.82 dB 0 dB 3 dB 6 dB 9 dB CONTROL BITS GAI25 0 0 0 1 1 GAI24 0 0 1 0 1 GAI23 0 1 1 1 1 GAI22 0 1 1 1 1 GAI21 0 1 1 1 1 GAI20 0 1 1 1 1
Table 45 Gain mode select (GASL); data bit D6 FUNCTION Difference value integration Fix value integration Table 46 Automatic control integration (HOLD); data bit D7 FUNCTION AGC active AGC integration hold (freeze) 16.4.9 SUBADDRESS 28 (DATA BYTE 071 to 064) CONTROL BIT HOLD 0 1 CONTROL BIT GASL 0 1
Table 47 White peak control WIPE CONTROL BITS DECIMAL WHITE PEAK LEVEL WIPE7 128 254 255 (white peak control off) 1 1 1 WIPE6 0 1 1 WIPE5 0 1 1 WIPE4 0 1 1 WIPE3 0 1 1 WIPE2 0 1 1 WIPE1 0 1 1 WIPE0 0 0 1
16.4.10 SUBADDRESS 29 (DATA BYTE 079 to 072) Table 48 Sync bottom control SBOT CONTROL BITS DECIMAL SYNC BOTTOM LEVEL SBOT7 1 254 1995 Oct 18 0 1 SBOT6 0 1 48 SBOT5 0 1 SBOT4 0 1 SBOT3 0 1 SBOT2 0 1 SBOT1 0 1 SBOT0 1 0
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
16.4.11 SUBADDRESS 2A (DATA BYTE 087 to 080); GAIN CONTROL ANALOG #2 Table 49 Static gain control channel 3 (GAI3); data bits D5 to D0 DECIMAL MULTIPLIER 0 15 31 47 63 GAIN (step size = 0.19 dB) -2.82 dB 0 dB 3 dB 6 dB 9 dB
SAA7110; SAA7110A
CONTROL BITS GAI35 0 0 0 1 1 GAI34 0 0 1 0 1 GAI33 0 1 1 1 1 GAI32 0 1 1 1 1 GAI31 0 1 1 1 1 GAI30 0 1 1 1 1
Table 50 Integration factor white peak (IWIP); data bits D7 and D6 FUNCTION Fast selection | | Slow selection CONTROL BITS IWIP1 = 0; IWIP0 = 0 IWIP1 = 0; IWIP0 = 1 IWIP1 = 1; IWIP0 = 0 IWIP1 = 1; IWIP0 = 1
16.4.12 SUBADDRESS 2B (DATA BYTE 095 to 088); GAIN CONTROL ANALOG #3 Table 51 Static gain control channel 4 (GAI4); data bits D5 to D0 DECIMAL MULTIPLIER 0 15 31 47 63 GAIN (step size = 0.19 dB) -2.82 dB 0 dB 3 dB 6 dB 9 dB CONTROL BITS GAI45 0 0 0 1 1 GAI44 0 0 1 0 1 GAI43 0 1 1 1 1 GAI42 0 1 1 1 1 GAI41 0 1 1 1 1 GAI40 0 1 1 1 1
Table 52 Integration factor normal gain (IGAI); data bits D7 and D6 FUNCTION Slow selection | | Fast selection 1995 Oct 18 49 CONTROL BITS IGAI1 = 0; IGAI0 = 0 IGAI1 = 0; IGAI0 = 1 IGAI1 = 1; IGAI0 = 0 IGAI1 = 1; IGAI0 = 1
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
16.4.13 SUBADDRESS 2C (DATA BYTE 103 to 096) Table 53 Mixer control #2 FUNCTION Two's complement channel 2 (TWO2); data bit D0 Unipolar Two's complement (normal mode) Two's complement channel 3 (TWO3); data bit D1 Unipolar Two's complement (normal mode) Clamping level select channel 2 (CLS2); data bit D4 CLL21 active CLL22 active Clamping level select channel 3 (CLS3); data bit D5 CLL31 active CLL32 active Clamping level select channel 4 (CLS4); data bit D7 CLL2n active CLL3n active 16.4.14 SUBADDRESS 2D (DATA BYTE 111 to 104) Table 54 Integration value gain (IVAL)
SAA7110; SAA7110A
CONTROL BITS
TWO2 = 0 TWO2 = 1
TWO3 = 0 TWO3 = 1
CLS2 = 0 CLS2 = 1
CLS3 = 0 CLS3 = 1
CLS4 = 0 CLS4 = 1
CONTROL BITS DECIMAL INTEGRATION VALUE GAIN IVAL7 1 255 16.4.15 SUBADDRESS 2E (DATA BYTE 119 to 112) Table 55 Blanking pulse VBLK-set (VBPS) DECIMAL MULTIPLIER 0 131(1) 156(2) Notes 1. Maximum for 60 Hz. 2. Maximum for 50 Hz. 1995 Oct 18 50 SET LINE NUMBER (step size = 2) 0 after rising edge of VS 262 after rising edge of VS 312 after rising edge of VS CONTROL BITS VBPS7 VBPS6 VBPS5 VBPS4 VBPS3 VBPS2 VBPS1 VBPS0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 IVAL6 0 1 IVAL5 0 1 IVAL4 0 1 IVAL3 0 1 IVAL2 0 1 IVAL1 0 1 IVAL0 1 1
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
16.4.16 SUBADDRESS 2F (DATA BYTE 127 to 120) Table 56 Blanking pulse VBLK-reset (VBPR) DECIMAL MULTIPLIER 0 131(1) 156(2) Notes 1. Maximum for 60 Hz. 2. Maximum for 50 Hz. 16.4.17 SUBADDRESS 30 (DATA BYTE 135 to 128) Table 57 ADCs gain control FUNCTION Fix gain ADC channel 2 (GAD2); data bits D1 and D0 0 dB 0.05 dB 0.10 dB 0.15 dB Gain ADC select channel 2 (GAS2); data bit D2 Fix gain via I2C-bus GAD2 Automatic gain via loop Fix gain ADC channel 3 (GAD3); data bits D4 and D3 0 dB 0.05 dB 0.10 dB 0.15 dB Gain ADC select channel 3 (GAS3); data bit D5 Fix gain via I2C-bus GAD3 Automatic gain via loop White peak mode select (WISL); data bit D6 Difference value integration Fix value integration RESET LINE NUMBER (step size = 2) 0 after rising edge of VS 262 after rising edge of VS 312 after rising edge of VS
SAA7110; SAA7110A
CONTROL BITS VBPR7 VBPR6 VBPR5 VBPR4 VBPR3 VBPR2 VBPR1 VBPR0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0
CONTROL BITS
GAD21 = 0; GAD20 = 0 GAD21 = 0; GAD20 = 1 GAD21 = 1; GAD20 = 0 GAD21 = 1; GAD20 = 1
GAS2 = 0 GAS2 = 1
GAD31 = 0; GAD30 = 0 GAD31 = 0; GAD30 = 1 GAD31 = 1; GAD30 = 0 GAD31 = 1; GAD30 = 1
GAS3 = 0 GAS3 = 1
WISL = 0 WISL = 1
1995 Oct 18
51
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
16.4.18 SUBADDRESS 31 (DATA BYTE 143 to 136) Table 58 Mixer control #3 FUNCTION Pulses I/O control (PULIO); data bit D0 HCL and HSY to input pins HCL and HSY to output pins Pin function switch (VBLKA); data bit D1 GPSW active (normal) VBLK test output active DMSD-SQP bypassed (SQPB); data bit D3 DMSD data to YUV output A/D data to YUV output for test purposes only (do not use) White peak slow up integration enable (WRSE); data bit D4 Hold in white peak mode Slow up integration with 1 value in H or V (dependent on WIRS) White peak slow up integration select (WIRS); data bit D5 Slow up integration with 1 value per line Slow up integration with 1 value per field Analog test select (AOSL); data bits D7 and D6 AOUT connected to ground AOUT connected to input AD2 AOUT connected to input AD3 AOUT connected to channel 4 16.4.19 SUBADDRESS 32 (DATA BYTE 151 to 144) Table 59 Integration value white peak (WVAL) DECIMAL INTEGRATION VALUE WHITE PEAK 1 127 (max.)
SAA7110; SAA7110A
CONTROL BITS
PULIO = 0 PULIO = 1
VBLKA = 0 VBLKA = 1
SQPB = 0 SQPB = 1
WRSE = 0 WRSE = 1
WRIS = 0 WRIS = 1
AOSL1 = 0; AOSL0 = 0 AOSL1 = 0; AOSL0 = 0 AOSL1 = 1; AOSL0 = 1 AOSL1 = 1; AOSL0 = 1
CONTROL BITS WVAL7 WVAL6 WVAL5 WVAL4 WVAL3 WVAL2 WVAL1 WVAL0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 1 1
1995 Oct 18
52
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
16.4.20 SUBADDRESS 33 (DATA BYTE 159 to 152) Table 60 Mixer control #4 FUNCTION Clock select AD2 (CAD2); data bit D2 LLC for test purposes only (do not use) LLC/2 Clock select AD3 (CAD3); data bit D3 LLC for test purposes only (do not use) LLC/2 Change sign bit UV data (CHSB); data bit D5 UV output unipolar UV output two's complement Output format select (OFTS); data bit D7 4 : 1 : 1 format 4 : 2 : 2 format 16.4.21 SUBADDRESS 34 (DATA BYTE 167 to 160) Table 61 Gain update level (GUDL; data bits D5 to D0 DECIMAL 0 7 >31 HYSTERESIS FOR 8-BIT GAIN 0 LSB 7 LSB off
SAA7110; SAA7110A
CONTROL BITS
CAD2 = 0 CAD2 = 1
CAD3 = 0 CAD3 = 1
CHSB = 0 CHSB = 1
OFTS = 0 OFTS = 1
CONTROL BITS UPDATE NEW GAIN - OLD GAIN GUDL5 GUDL4 GUDL3 GUDL2 GUDL1 GUDL0 >0 >7 always 0 0 1 0 0 X 0 0 X 0 1 X 0 1 X 0 1 X
Table 62 MUXC phase delay (MUD2); data bits D7 and D6 FUNCTION No phase delay 1 LLC cycle phase delay for CLAA path 2 LLC cycle phase delay for CLAA path 3 LLC cycle phase delay for CLAA path CONTROL BIT MUD MUD2 = 0; MUD1 = 0 MUD2 = 0; MUD1 = 1 MUD2 = 1; MUD1 = 0 MUD2 = 1; MUD1 = 1
1995 Oct 18
53
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
17 SOURCE SELECTION MANAGEMENT
AINS4 AIND4 AI41 AI42 REFS4 CLAMP CLS4 clamp up/down MX340 AINS3 AIND3 AI31 AI32 MX341 REFS3 CLAMP GAIN3 AAF3 ADC3 GAIN4 AAF4
SAA7110; SAA7110A
CLS3 CLAMP CON3 CLL32 CLL31
CHRS v BYPS CHROMA CSEL
MX240 AINS2 AIND2 AI21 AI22 MX241 REFS2 CLAMP clamp up/down CLAMP CON2 CLS2 CLL22 CLL21 GAIN2 AAF2 ADC2 YSEL LUMA
REF128 GAI4 GAIN CON
MGC839
GAI3
GAI2 GACO
All switch control bits set to LOW.
Fig.20 Source selection overview.
Table 63 Source selection management examples EXAMPLE 1 INPUT SIGNAL AIN21 AIN22 AIN31 AIN32 AIN41 AIN42 CVBS1 CVBS2 CVBS3 CVBS4 CVBS5 CVBS6 MODE 0 1 2 3 4 5 SIGNAL CVBS1 C2 Y2 C3 Y3 CVBS6 MODE 0 7 7 8 8 5 SIGNAL Y1 C2 Y2 C3 Y3 C1 MODE 6 7 7 8 8 6 SIGNAL Y1 CVBS2 CVBS3 CVBS4 CVBS5 C1 MODE 6 1 2 3 4 6 EXAMPLE 2 EXAMPLE 3 EXAMPLE 4
handbook, full pagewidth
AI41 AI42 AI31 AI32 AI21 AI22
AD3 CHROMA AD2 LUMA
MGC840
Fig.21 Mode 0; CVBS1.
1995 Oct 18
54
ll pagewidth
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
SAA7110; SAA7110A
handbook, full pagewidth
AI41 AI42 AI31 AI32 AI21 AI22
AD3 CHROMA AD2 LUMA
MGC841
Fig.22 Mode 1; CVBS2.
handbook, full pagewidth
AI41 AI42 AI31 AI32 AI21 AI22
AD3 CHROMA AD2 LUMA
MGC842
Fig.23 Mode 2; CVBS3.
handbook, full pagewidth
AI41 AI42 AI31 AI32 AI21 AI22
AD3 CHROMA AD2 LUMA
MGC843
Fig.24 Mode 3; CVBS4.
handbook, full pagewidth
AI41 AI42 AI31 AI32 AI21 AI22
AD3 CHROMA AD2 LUMA
MGC844
Fig.25 Mode 4; CVBS5.
1995 Oct 18
55
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
SAA7110; SAA7110A
handbook, full pagewidth
AI41 AI42 AI31 AI32 AI21 AI22
AD3 CHROMA AD2 LUMA
MGC845
Fig.26 Mode 5; CVBS6.
handbook, full pagewidth
AI41 AI42 AI31 AI32 AI21 AI22
AD3 CHROMA AD2 LUMA
MGC846
Fig.27 Mode 6; Y1 + C1.
handbook, full pagewidth
AI41 AI42 AI31 AI32 AI21 AI22
AD3 CHROMA AD2 LUMA
MGC847
Fig.28 Mode 7; Y2 + C2.
handbook, full pagewidth
AI41 AI42 AI31 AI32 AI21 AI22
AD3 CHROMA AD2 LUMA
MGC848
Fig.29 Mode 8; Y3 + C3.
1995 Oct 18
56
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
Table 64 I2C-bus control CONTROL INPUT(1) Subaddress 20 AIND4 AIND3 AIND2 FUSE1 FUSE0 AINS4 AINS3 AINS2 Subaddress 21 VBCO MS34 MX241 MX240 MS24 REFS4 REFS3 REFS2 Subaddress 22 GACO1 GACO0 CSEL YSEL MUYC CLTS MX341 MX340 Subaddress 2C CLS4 GABL CLS3 CLS2 4LSB BYPS X 0 X 0 0011 0 X - X 0 - 0 X - 0 X - 0 X - 0 X - 0 1 - 0 X - 0 1 - 0 X - 0 1 - 1 0 - 1 0 1 X 0 0 0 X X 0 1 X 0 - - X X 1 0 X 1 - - 0 1 1 0 X 1 - - 0 1 1 1 X 1 - - 1 0 1 1 X 1 - - 1 0 0 1 0 0 - - 1 0 0 0 0 0 0 1 1 0 - - 0 0 - 1 1 0 - - X X - 1 0 1 - - X X - 1 0 1 - - X X - 0 1 1 - - X X - 0 1 1 - - 0 0 - 0 1 0 1 1 0 1 1 X X 1 1 1 0 - - X X 0 1 0 1 - - X 1 X 1 0 1 - - X 0 X 0 1 1 - - 1 X X 0 1 1 - - 0 X X 0 1 0 - - 0 0 1 MODE 0 1 2 3 4 5 6
SAA7110; SAA7110A
7
8
9 - - - - - - - - - - - - - - - - - - - - 0 0 - - - - - - 0011 - - -
1 0 0 - - X 1 0 - - 0 0 - 1 0 0
0 0 1 - - 1 0 X - - 1 1 - 0 0 1
1 0 1 1 - - 0 1
1 1 0 0 - - 0 1
X - 0 1 - 1
0 - 1 X - 1
Subaddresses SU 20H 21H D9H 16H D8H 16H BAH 05H B8H 05H 7CH 03H 78H 03H 59H 12H 9AH 14H 3CH 21H
1995 Oct 18
57
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
SAA7110; SAA7110A
CONTROL INPUT(1) 22H 2CH 06H 30H(2) Notes
MODE 0 40H 03H 44H 1 40H 03H 44H 2 91H 03H 60H 3 91H 03H 60H 4 D2H 83H 60H 5 D2H 83H 60H 6 42H A3H 44H 7 B1H 13H 1XXXXXXX 60H 44H 8 C1H 23H 9 - - - -
0XXXXXXX
1. CLL21 = 65d, CLL22 = 128d, CLL31 = 65d, CLL32 = 128d, GAI4 = 15d, GAI3 = 15dGAI2 = 15d; X set 0. 2. Optional: values for AD gain (+2 LSB's gain resolution) active [not active: for all modes 40H]. 18 ANTI-ALIAS FILTER GRAPHS
handbook, full pagewidth
+3
MGC849
A (dB)
-3
-9 (1)
-15
-21 (2) -27
-33
-39
0
2
4
6
8
10
12
14
f (MHz)
16
(1) 50 Hz. (2) 60 Hz.
Fig.30 Anti-alias filter graph for SAA7110A.
1995 Oct 18
58
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
SAA7110; SAA7110A
handbook, full pagewidth
+3
MGC850
A (dB)
-3
-9
-15 (4) (3) (2) (1)
-21
-27
-33
-39
0
5
10
15
20
25
f (MHz)
30
(1) 50 HZ, AFCCS = 0, LLC = 29.50 MHz. (2) 50 HZ, AFCCS = 1, LLC = 29.50 MHz. (3) 60 HZ, AFCCS = 0, LLC = 24.54 MHz. (3) 60 HZ, AFCCS = 1, LLC = 24.54 MHz.
Fig.31 Anti-alias filter graph for SAA7110.
19 CORING FUNCTION 19.1 Coring function adjustment by subaddress 06H to affect band filter output adjustment
handbook, halfpage
+64
MGC851
The thresholds are related to the 13-bit word width in the luminance processing part and influence the 1 to 3 LSB (Yo to Y2) with respect to the 8-bit luminance output. Table 65 CORI control settings a, b and c of Fig.32 CONTROL BITS CORI1 a b c 0 1 1 CORI0 1 0 1
c +32 b a 0 a b c
-32
-64 -64
-32
0
+32
+64
Fig.32 Coring function.
1995 Oct 18
59
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
20 LUMINANCE FILTER GRAPHS
SAA7110; SAA7110A
MGC852
handbook, full pagewidth
18
VY (dB) 6 63H 73H 53H 43H 40H
-6
43H 53H 73H 63H 40H
-18
-30
0
2
4
6
fY (MHz)
8
Fig.33 Luminance control: SU06H, 50 Hz/CVBS mode, prefilter on and coring off (40 to 63H).
MGC853
handbook, full pagewidth
18
VY (dB) 6 43H 42H 41H 40H
43H 42H 41H 40H
-6
-18
-30
0
2
4
6
f
8 Y (MHz)
Fig.34 Luminance control: SU06H, 50 Hz/CVBS mode, prefilter on and coring off (40 to 43H).
1995 Oct 18
60
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
SAA7110; SAA7110A
MGC854
handbook, full pagewidth
18
VY (dB) 6 23H 33H 13H 03H 00H
-6
03H 13H 33H 23H 00H
-18
-30
0
2
4
6
fY (MHz)
8
Fig.35 Luminance control: SU06H, 50 Hz/CVBS mode, prefilter off and coring off.
MGC855
handbook, full pagewidth
18
VY (dB) 6 83H 82H 81H 80H
-6
-18
-30
0
2
4
6 f Y (MHz)
8
Fig.36 Luminance control: SU06H, 50 Hz/Y + C mode, prefilter off and coring off.
1995 Oct 18
61
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
SAA7110; SAA7110A
MGC856
handbook, full pagewidth
18
VY (dB) 6 C3H C2H C1H C0H
-6
-18
-30
0
2
4
6
fY (MHz)
8
Fig.37 Luminance control: SU06H, 50 Hz/Y + C mode, prefilter on and coring off.
MGC857
handbook, full pagewidth
18
VY (dB) 6 63H 73H 53H 43H 40H -6
43H 53H 73H 63H 40H
-18
-30
0
2
4
fY (MHz)
6
Fig.38 Luminance control: SU06H, 60 Hz/CVBS mode, prefilter on and coring off.
1995 Oct 18
62
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
SAA7110; SAA7110A
MGC858
handbook, full pagewidth
18
VY (dB) 6 43H 42H 41H 40H -6 43H 42H 41H 40H
-18
-30
0
2
4
fY (MHz)
6
Fig.39 Luminance control: SU06H, 60 Hz/CVBS mode, prefilter on and coring off.
MGC859
handbook, full pagewidth
18
VY (dB) 6
-6
23H 33H 13H 03H 00H
03H 13H 33H 23H 00H
-18
-30
0
2
4
fY (MHz)
6
Fig.40 Luminance control: SU06H, 60 Hz/CVBS mode, prefilter off and coring off.
1995 Oct 18
63
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
SAA7110; SAA7110A
MGC860
handbook, full pagewidth
18
VY (dB) 6 83H 82H 81H 80H
-6
-18
-30
0
2
4
6
fY (MHz)
8
Fig.41 Luminance control: SU06H, 60 Hz/Y + C mode, prefilter off and coring off.
MGC861
handbook, full pagewidth
18
VY (dB) 6
C3H C2H C1H C0H
-6
-18
-30
0
2
4
6
f (MHz) Y
8
Fig.42 Luminance control: SU06H, 60 Hz/Y + C mode, prefilter on and coring off.
1995 Oct 18
64
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
21 I2C-BUS START SET-UP
SAA7110; SAA7110A
The values shown in Table 66 are optimized for the EBU colour bar (100% white and 75% chrominance amplitude) signal. The decoder output signal level fulfils the CCIR 601 specification. The input of 100% colour bar level is possible, but the signal (white) peak function reduces the digital luminance output. With a different set-up it is possible to proceed 100% colour bar signal without luminance colour bar reduction. The method is to modify the AD input range for this input level by reducing the gain reference value (SBOT > 06h) and adjusting the digital Y output level with contrast and brightness control. Table 66 I2C-bus start set-up SU 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 NAME IDEL7 to IDEL0 HSYB7 to HSYB0 HSYS7 to HSYS0 HCLB7 to HCLB0 HCLS7 to HCLS0 HPHI7 to HPHI0 BYPS, PREF, BPSS1 to BPSS0, CORI1 to CORI0, APER1 to APER0 HUEC7 to HUEC0 CKTQ4 to CKTQ0, XXX CKTS4 to CKTS0, XXX PLSE7 to PLSE0 SESE7 to SESE0 COLO, LFIS1 to LFIS0, XXXXX VTRC, XXX, RTSE, HRMV, SSTB, SECS HPLL, XX, OEHV, OEYC, CHRS, X, GPSW AUFD, FSEL, SXCR, SCEN, X, YDEL2 to YDEL0 XXXXX, HRFS, VNOI1 to VNOI0 CHCV7 to CHCV0 PAL CHCV7 to CHCV0 NTSC SATN7 to SATN0 CONT7 to CONT0 HS6B7 to HS6B70 HS6S7 to HS6S0 HC6B7 to HC6B0 HC6S7 to HC6S0 HP6I7 to HP6I0 BRIGI7 to BRIG0 FUNCTION increment delay horizontal sync (HSY) begin 50 Hz horizontal sync (HSY) stop 50 Hz horizontal clamp (HCL) begin 50 Hz horizontal clamp (HCL) stop 50 Hz horizontal sync after PHI1 50 Hz luminance control hue control colour killer threshold PAL colour killer threshold SECAM PAL switch sensitivity SECAM switch sensitivity gain control chrominance standard/mode control I/O and clock control control #1 control #2 BINARY 7 0 0 0 1 1 1 0 0 1 1 0 0 0 0 0 1 X 0 0 0 0 0 0 1 1 1 1 6 1 0 0 1 0 1 0 0 1 1 1 1 0 X X 0 X 1 0 1 1 1 0 1 1 1 0 5 0 1 0 1 1 1 0 0 1 1 1 1 0 X X 0 X 0 1 0 0 0 0 1 0 1 0 4 0 1 0 0 1 1 0 0 1 1 0 0 X X 1 1 X 1 0 0 0 0 1 1 1 1 0 3 1 1 1 1 1 0 0 0 1 1 0 0 X 0 1 X X 1 1 0 0 0 1 1 1 0 1 2 1 1 1 1 1 0 0 0 X X 0 0 X 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 X X 0 0 X 1 X 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 1 1 1 0 0 0 X X 0 0 X 0 0 0 0 1 0 0 0 0 0 1 0 0 1 HEX start 4C 3C 0D EF BD F0 00 00 F8 F8 60 5B 00 06 18 90 00 59 2C 40 46 42 1A FF DA F0 8B
chrominance gain reference chrominance saturation luminance contrast horizontal sync (HSY) begin 60 Hz horizontal sync (HSY) stop 60 Hz horizontal clamp (HCL) begin 60 Hz horizontal clamp (HCL) stop 60 Hz horizontal sync after PHI1 60 Hz luminance brightness 65
1995 Oct 18
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
SAA7110; SAA7110A
SU
NAME
FUNCTION
BINARY 7 6 5 4 3 2 1 0
HEX start
1A-1F reserved AIND4, AIND3, AIND2, 20 FUSE1 to FUSE0, AINS4, AINS3, AINS2 VBCO, MS34, 21 MX241 to MX240, MS24, REFS4, REFS3, REFS2 GACO1 to GACO0, CSEL, 22 YSEL, MUYC, CLTS, MX341 to MX340 23 CLL217 to CLL210 24 CLL227 to CLL220 25 CLL317 to CLL310 26 CLL327 to CLL320 HOLD, GASL, 27 GAI25 to GAI20 28 WIPE7 to WIPE0 29 SBOT7 to SBOT0 IWIP1 to IWIP0, 2A GAI35 to GAI30 IGAI1 to IGAI0, 2B GAI45 to GAI40 CLS4, X, CLS3, CLS2, 2C TWO3, TWO2 2D IVAL7 to IVAL0 VBPS7 to VBPS0; 50 Hz 2E VBPS7 to VBPS0; 60 Hz VBPR7 to VBPR0; 50 Hz 2F VBPR7 to VBPR0; 60 Hz X, WISL, GAS3, 30 GAD31 to GAD30, GAS2, GAD21 to GAD20 AOSL1 to AOSL0, WIRS, 31 WRSE, SQPB, X, VBLKA, PULIO 32 WVAL7 to WVAL0 OFTS, X, CHSB, X, CAD3, 33 CAD2, XX MUD2, MUD1, 34 GUDL5 to GUDL0 21.1 Remarks to Table 66
analog control #1
1
1
0
1
1
0
0
1
D9
analog control #2
0
0
0
1
0
1
1
0
16
mixer control #1 clamping level control channel 21 clamping level control channel 22 clamping level control channel 31 clamping level control channel 32 gain control analog #1 white peak control sync bottom control gain control analog #2 gain control analog #3 mixer control #2 integration value gain vertical blanking pulse SET vertical blanking pulse RESET
0 0 1 0 1 0 1 0 1 0 0 0 1 1 0 0 X
1 1 0 1 0 1 1 0 1 0 X 0 0 0 0 0 1
0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0
0 0 0 0 0 1 1 0 1 1 X 0 1 0 0 0 0
0 0 0 0 0 1 1 0 1 1 X 0 0 0 0 0 0
0 0 0 0 0 1 1 0 1 1 1 0 1 0 1 1 0
0 1 0 1 0 1 0 1 1 1 1 1 0 1 1 1 0
40 41 80 41 80 4F FE 01 CF 0F 03 01 9A 81 03
ADCs gain control
44
mixer control #3 integration value white peak mixer control #4 gain update level
0 0 1 0
1 0 X 0
1 0 0 0
1 0 X 0
0 0 1 0
X* 0 1 0
0 1 X 1
1 0 X 1
71 02 8C 03
Values recommended for a CVBS (PAL or NTSC) signal, input AI21 via A/D channel 2 (MODE 0), and 4 : 2 : 2 CCIR output signal level; all X values must be set LOW, X* value is don't care; HPHI and HP6I are application dependent.
1995 Oct 18
66
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
22 APPLICATION INFORMATION
handbook, full pagewidth
VDD VDDA C10 100 nF C9 100 nF C8 100 nF C7 VSSA C6 AI42 R6 10 nF 75 VSSA C5 AI41 R5 10 nF 75 VSSA C24 AI32 R4 10 nF 75 VSSA C3 AI31 R3 10 nF 75 VSSA C2 AI22 R2 10 nF 75 VSSA C1 AI21 R1 10 nF 75 VSSA 42 38 VDD SCL SDA FEIN (MUXC) R7 1 k VSS Q1(26.8 MHz) XTALO 65 66 10 L1 H C16 1 nF XTALI C17 C18 25 18 14 10 22 67 51 43 35 28 4 2 1 789 R8 CGCE 1 k 6 5 63 33 41 3 23 64 39 40 29 30 31 32 26 36 37 21 19 17 55 56 57 58 59 60 61 62 15 13 11 45 46 47 48 49 50 53 54 100 nF 24 20 16 12 68 52 44 34 27 VDD1 C15 100 nF VDD2 C14 100 nF VDD3 C13 100 nF VDD4 C12 100 nF VDD5 C11 100 nF
SAA7110; SAA7110A
VSS
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Y7 to Y0
UV7 UV6 UV5 UV4 UV3 UV2 UV1 UV0 UV7 to UV0
SAA7110 SAA7110A
HREF HS VS RTCO AOUT GPSW (VBLK) PLIN (HL) ODD (VL) LLC LLC2 CREF RESET LFCO HCL HSY
MGC862
10 pF 10 pF SA AP SP VSS VSSA VSS VSS i.c. i.c. i.c.
Unused analog inputs should not be connected.
Fig.43 Application diagram.
1995 Oct 18
67
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40 FEIN (MUXC) 1 k R7 CGCE 33 63 30 29 31 LLC2 LLC CREF RESET LFCO ODD (VL) n.c. XTALO Q1 (26.8 MHZ) XTALI 10 H C16 1 nF C17 10 pF C18 10 pF VSS VDDA VDDD LFCO2 LFCO RESN CREF LLCA 8,17 5 R10 1 k MS CE C21 100 nF C22 100 nF LFCOSEL 1 2 16 3 4 6, 9 13, 18 19 11 12 15 7 66 25 18 14 10 22 67 51 VSS 43 VSS 35 VSS 28 VSS 4 SA VSS 2 AP 1 SP i.c. VSSA VSS i.c. i.c. RESET CREF 7 8 9 36 37 L1 HCL HSY
Philips Semiconductors
One Chip Front-end 1 (OCF1)
SAA7110 SAA7110A
32 26
65
VSSA0 VSSA2 VSSA3 VSSA4 VSS(S) VSS
The OCF1 supports for special applications the use of an external CGC (SAA7197). For normal operation the built-in CGC fulfils all requirements.
Fig.44 Application diagram with external Clock Generator Circuit (CGC).
handbook, full pagewidth
68
SAA7197
10
14
20 LLC2B
PORD VSSA VSSD 0.1 F
SAA7110; SAA7110A
C20
LLC2A LLCB
MGC863
Product specification
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
SAA7110; SAA7110A
23 START-UP, SOURCE SELECT AND STANDARD DETECTION FLOW EXAMPLE
handbook, full pagewidth
power on
start source select
initialization
mode 0 set-up
REFS active
precharge clamping capacitor
mode select
mode 0 to 7
REFS off
without standard routine clamp active
standard automatic ?status byte?
B&W50? yes = XX0XXX00 B&W60? yes = XX1XXX00 NTSC? yes = XX1XXXXX SECAM? yes = XX0XXX01
yes
B&W50?
no
yes
B&W60?
no
yes
NTSC?
no
PAL set-up
no B&W50 set-up NTSC set-up
SECAM?
yes
B&W60 set-up
SECAM set-up
stop
MGC864
Fig.45 Software flow example.
1995 Oct 18
69
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
23.1 CODE 0 STARTUP and STANDARD Procedure #SECAM SUB 0D WRITE 07 PRINT "SECAM" GOTO STOP #STOP 23.2
SAA7110; SAA7110A
SLAVE 9C !OCF1 NTSC-setup SUB 00 WRITE 4C 3C 0D EF BD F0 00 00 F8 F8 60 60 00 06 18 90 00 2C 40 46 42 1A FF DA F0 8B 00 00 00 00 00 00 D9 17 40 41 80 41 80 4F FE 01 CF 0F 03 01 81 03 44 75 01 8C 03 SUB 21 WRITE 16 !REFS OFF CLAMP AKTIV READ 1 !Status? #STANDARD IF 1 @XX0XXX00 !NO COLOR THEN GOTO BW_50Hz ENDIF IF 1 @XX1XXX00 !NO COLOR THEN GOTO BW_60Hz ENDIF SUB 06 WRITE 00 ENDIF IF 1 @XX1XXXXX !60Hz THEN GOTO NTSC ENDIF IF 1 @XX0XXXXX !50Hz THEN GOTO PAL ENDIF #BW_50Hz PRINT "BLACK&WHITE" SUB 06 WRITE 80 SUB 2E WRITE 9A !VBPS GOTO STOP #BW_60Hz PRINT "BLACK&WHITE" SUB 06 WRITE 80 SUB 2E WRITE 81 !VBPS GOTO STOP #NTSC SUB 0D WRITE 06 !SECS -> 0 SUB 11 WRITE 2C !CHCV SUB 2E WRITE 81 !VBPS PRINT "NTSC" GOTO STOP #PAL SUB 0D WRITE 06 !SECS -> 0 SUB 11 WRITE 59 !CHCV SUB 2E WRITE 9A !VBPS PAUSE %150 !150ms IF 1 @XX0XXX01 THEN GOTO SECAM ELSE PRINT "PAL" GOTO STOP 1995 Oct 18 70
!SECS -> 1
MODE 0 Source Select Procedure 00 D9 17 40 03 44 75 16 !OCF1 !CVBS MODE 0 !AI21 ACTIVE !REFS ON !AD2->LUMA and CHROMA !CLAMP SELECT !Gain AD2 active !AOSL -> 01b !REFS OFF CLAMP AKTIV
SLAVE 9C SUB 06 WRITE SUB 20 WRITE SUB 21 WRITE SUB 22 WRITE SUB 2C WRITE SUB 30 WRITE SUB 31 WRITE SUB 21 WRITE 23.3
MODE 1 Source Select Procedure 00 D8 17 40 03 44 75 16 !OCF1 !CVBS MODE 1 !AI22 ACTIVE !REFS ON !AD2->LUMA and CHROMA !CLAMP SELECT !Gain AD2 active !AOSL -> 01b !REFS OFF CLAMP AKTIV
SLAVE 9C SUB 06 WRITE SUB 20 WRITE SUB 21 WRITE SUB 22 WRITE SUB 2C WRITE SUB 30 WRITE SUB 31 WRITE SUB 21 WRITE 23.4
MODE 2 Source Select Procedure 00 BA 07 91 03 60 B5 05 !OCF1 !CVBS MODE 2 !AI31 ACTIVE !REFS ON !AD3->LUMA and CHROMA !CLAMP SELECT !Gain AD3 active !AOSL -> 10b !REFS OFF CLAMP AKTIV
SLAVE 9C SUB 06 WRITE SUB 20 WRITE SUB 21 WRITE SUB 22 WRITE SUB 2C WRITE SUB 30 WRITE SUB 31 WRITE SUB 21 WRITE 23.5
MODE 3 Source Select Procedure 00 B8 07 91 03 60 B5 05 !OCF1 !CVBS MODE 3 !AI32 ACTIVE !REFS ON !AD3->LUMA and CHROMA !CLAMP SELECT !Gain AD3 active !AOSL -> 10b !REFS OFF CLAMP AKTIV
SLAVE 9C SUB 06 WRITE SUB 20 WRITE SUB 21 WRITE SUB 22 WRITE SUB 2C WRITE SUB 30 WRITE SUB 31 WRITE SUB 21 WRITE
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
23.6 MODE 4 Source Select Procedure 00 7C 07 D2 83 60 B5 03 !OCF1 !CVBS MODE 4 !AI41 ACTIVE !REFS ON !AD3->LUMA and CHROMA !CLAMP SELECT !Gain AD3 active !AOSL -> 10b !REFS OFF CLAMP AKTIV SUB SUB SUB SUB 2C 30 31 21 WRITE WRITE WRITE WRITE 23 44 75 21
SAA7110; SAA7110A
!CLAMP SELECT !Gain AD2 active !AOSL -> 01 !REFS OFF CLAMP AKTIV
SLAVE 9C SUB 06 WRITE SUB 20 WRITE SUB 21 WRITE SUB 22 WRITE SUB 2C WRITE SUB 30 WRITE SUB 31 WRITE SUB 21 WRITE 23.7
MODE 5 Source Select Procedure 00 78 07 D2 83 60 B5 03 !OCF1 !CVBS MODE 5 !AI41 ACTIVE !REFS ON !AD3->LUMA and CHROMA !CLAMP SELECT !Gain AD3 active !AOSL -> 10b !REFS OFF CLAMP AKTIV
SLAVE 9C SUB 06 WRITE SUB 20 WRITE SUB 21 WRITE SUB 22 WRITE SUB 2C WRITE SUB 30 WRITE SUB 31 WRITE SUB 21 WRITE 23.8
MODE 6 Source Select Procedure 80 59 17 42 A3 44 75 12 !OCF1 !Y+C MODE 6 !AI21=Y, AI42=C !REFS ON !AD2->LUMA, AD3->CHR !CLAMP SELECT !Gain AD2 active !AOSL -> 01 !REFS OFF CLAMP AKTIV
SLAVE 9C SUB 06 WRITE SUB 20 WRITE SUB 21 WRITE SUB 22 WRITE SUB 2C WRITE SUB 30 WRITE SUB 31 WRITE SUB 21 WRITE 23.9
MODE 7 Source Select Procedure 80 9A 17 B1 13 60 B5 14 !OCF1 !Y+C MODE 7 !AI31=Y, AI22=C !REFS ON !AD3->LUMA, AD2->CHR !CLAMP SELECT !Gain AD3 active !AOSL -> 10b !REFS OFF CLAMP AKTIV
SLAVE 9C SUB 06 WRITE SUB 20 WRITE SUB 21 WRITE SUB 22 WRITE SUB 2C WRITE SUB 30 WRITE SUB 31 WRITE SUB 21 WRITE
23.10 MODE 8 Source Select Procedure SLAVE 9C SUB 06 WRITE SUB 20 WRITE SUB 21 WRITE SUB 22 WRITE 1995 Oct 18 80 3C 27 C1 !OCF1 !Y+C MODE 8 !AI41=Y, AI32=C !REFS ON !AD2->LUMA, AD3->CHR 71
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
24 PACKAGE OUTLINE PLCC68: plastic leaded chip carrier; 68 leads
SAA7110; SAA7110A
SOT188-2
eD y 60 61 X 44 43 Z E A
eE
bp b1 wM
68
1
pin 1 index e
E
HE A A4 A1 (A 3)
k
9
27
k1
Lp detail X
10 e D HD
26 ZD B
vM A
vMB 0 5 scale 10 mm
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions) UNIT
mm
A
4.57 4.19
A1 min.
0.51
A3
0.25
A4 max.
3.30
bp
0.53 0.33
b1
0.81 0.66
D (1)
E (1)
e
eD
eE
HD
HE
k
k1 max.
0.51
Lp
1.44 1.02
v
0.18
w
0.18
y
0.10
Z D(1) Z E (1) max. max.
2.16 2.16
24.33 24.33 23.62 23.62 25.27 25.27 1.22 1.27 24.13 24.13 22.61 22.61 25.02 25.02 1.07
45 o
0.180 inches 0.020 0.01 0.165
0.930 0.930 0.995 0.995 0.048 0.057 0.021 0.032 0.958 0.958 0.020 0.05 0.007 0.007 0.004 0.085 0.085 0.13 0.890 0.890 0.985 0.985 0.042 0.040 0.013 0.026 0.950 0.950
Note 1. Plastic or metal protrusions of 0.01 inches maximum per side are not included. OUTLINE VERSION SOT188-2 REFERENCES IEC 112E10 JEDEC MO-047AC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-03-11
1995 Oct 18
72
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
25 SOLDERING 25.1 Introduction 25.3
SAA7110; SAA7110A
Wave soldering
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 25.2 Reflow soldering
Wave soldering techniques can be used for all PLCC packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 25.4 Repairing soldered joints
Reflow soldering techniques are suitable for all PLCC packages. The choice of heating method may be influenced by larger PLCC packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9398 510 63011). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C.
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1995 Oct 18
73
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
26 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA7110; SAA7110A
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 27 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 28 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1995 Oct 18
74
Philips Semiconductors
Product specification
One Chip Front-end 1 (OCF1)
NOTES
SAA7110; SAA7110A
1995 Oct 18
75
Philips Semiconductors - a worldwide company
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Internet: http://www.semiconductors.philips.com/ps/ For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-2724825 SCD44 (c) Philips Electronics N.V. 1995
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
483061/1500/01/pp76 Document order number: Date of release: 1995 Oct 18 9397 750 00368

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